tqm8xx.patch

linux交叉编译环境个软件和内核的补丁。

+ diff -u linux-2.2.13/Makefile.ORIG linux-2.2.13/Makefile
--- linux-2.2.13/Makefile.ORIG	Sat Oct 23 00:40:01 1999
+++ linux-2.2.13/Makefile	Sun Jan  9 16:05:35 2000
@@ -3,7 +3,8 @@
 SUBLEVEL = 13
 EXTRAVERSION =
 
-ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
+#ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
+ARCH := ppc
 
 .EXPORT_ALL_VARIABLES:
 
@@ -18,7 +19,7 @@
 HOSTCC  	=gcc
 HOSTCFLAGS	=-Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
 
-CROSS_COMPILE 	=
+CROSS_COMPILE 	= powerpc-linux-
 
 AS	=$(CROSS_COMPILE)as
 LD	=$(CROSS_COMPILE)ld
+ diff -u linux-2.2.13/arch/ppc/8xx_io/commproc.c.ORIG linux-2.2.13/arch/ppc/8xx_io/commproc.c
--- linux-2.2.13/arch/ppc/8xx_io/commproc.c.ORIG	Fri Oct 22 23:25:42 1999
+++ linux-2.2.13/arch/ppc/8xx_io/commproc.c	Sun Jan  9 16:05:35 2000
@@ -58,7 +58,9 @@
 	volatile immap_t	 *imp;
 	volatile cpm8xx_t	*commproc;
 	pte_t			*pte;
+#ifdef CONFIG_UCODE_PATCH
 	extern void	cpm_load_patch(immap_t *);
+#endif
 
 	imp = (immap_t *)IMAP_ADDR;
 	commproc = (cpm8xx_t *)&imp->im_cpm;
+ diff -u linux-2.2.13/arch/ppc/8xx_io/commproc.h.ORIG linux-2.2.13/arch/ppc/8xx_io/commproc.h
--- linux-2.2.13/arch/ppc/8xx_io/commproc.h.ORIG	Sat Oct 23 01:14:48 1999
+++ linux-2.2.13/arch/ppc/8xx_io/commproc.h	Sun Jan  9 19:28:20 2000
@@ -397,7 +397,171 @@
  */
 #define SICR_ENET_MASK	((uint)0x000000ff)
 #define SICR_ENET_CLKRT	((uint)0x0000003d)
-#endif
+#endif	/* CONFIG_MBX */
+
+
+#if (defined(CONFIG_TQM860) || (defined(CONFIG_TQM8xxL) && defined(CONFIG_MPC860)))
+/*
+ * Port configuration for the TQ Systems TQM860 and TQM860L modules.
+ *
+ * Port A:
+ *
+ * Signal   PAR     DIR     ODR     DAT     Function
+ *  PA 0    0       1       -       -       -> SENSRST
+ *  PA 1    0       0       -       -       <- BENDE
+ *  PA 2    0       1       -       -       -> STREPP
+ *  PA 3    0       1       -       -       -> LED1
+ *  -------------------------------------
+ *  PA 4    0       1       -       -       -> LED2
+ *  PA 5    1       0       -       -       TCLK (CLK3) for Ethernet
+ *  PA 6    0       0       -       -          (not used)
+ *  PA 7    1       0       -       -       RCLK (CLK1) for Ethernet
+ *  -------------------------------------
+ *  PA 8    0       0       -       -       <- SWITCH1
+ *  PA 9    0       1       -       -       -> CONF_DCK
+ *  PA 10   0       1       -       -       -> COM_SEL
+ *  PA 11   0       0       -       -          (not used)
+ *  -------------------------------------
+ *  PA 12   1       0       -       -       TXD for Com 2    (SCC2)
+ *  PA 13   1       0       -       -       RXD for Com 2    (SCC2)
+ *  PA 14   1       0       -       -       TXD for Ethernet (SCC1)
+ *  PA 15   1       0       -       -       RXD for Ethernet (SCC1)
+ */
+
+#define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
+#define PA_ENET_TXD     ((ushort)0x0002)	/* PA 14 */
+#define PA_ENET_TCLK    ((ushort)0x0400)	/* PA  5 */
+#define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
+
+/*
+ * Port C:
+ *
+ * Signal   PAR     DIR     SO      DAT     Function
+ * PC 0     0       0       0       -          (not usable)
+ * PC 1     0       0       0       -          (not usable)
+ * PC 2     0       0       0       -          (not usable)
+ * PC 3     0       0       0       -          (not usable)
+ *  -------------------------------------
+ * PC 4     0       1       0       -       -> CONF_DON (LED on old board)
+ * PC 5     0       0       0       -       <- INIT_DONE
+ * PC 6     0       0       0       -       <- CNFSTAT
+ * PC 7     0       0       0       -       -> ETH-LOOP
+ *  -------------------------------------
+ * PC 8     0       0       1       -       CD  for COM2     (SCC2)
+ * PC 9     0       0       1       -       CTS for COM2     (SCC2)
+ * PC 10    0       0       1       -       CD  for Ethernet (SCC1)
+ * PC 11    0       0       1       -       CTS for Ethernet (SCC1)
+ *  -------------------------------------
+ * PC 12    0       0       0       -       -> FPGA_OE
+ * PC 13    0       0       0       -       -> FPGA_CLR
+ * PC 14    0       0       0       -          (not used)
+ * PC 15    *       *       0       -       TENA/RTS for Ethernet
+ */
+
+#define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
+#define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
+#define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x00000026)
+
+#endif	/* CONFIG_TQM860, TQM860L */
+
+
+#if (defined(CONFIG_TQM8xxL) && !defined(CONFIG_MPC860))
+/*
+ * Port configuration for the TQ Systems TQM8xxL modules except TQM860L
+ *
+ * Port A:
+ *
+ * Signal   PAR     DIR     ODR     DAT     Function
+ *  PA 0    0       0       -       -
+ *  PA 1    0       0       -       -
+ *  PA 2    0       0       -       -
+ *  PA 3    0       0       -       -
+ *  -------------------------------------
+ *  PA 4    0       0       -       -
+ *  PA 5    1       0       -       -       TCLK (CLK3) for Ethernet
+ *  PA 6    0       0       -       -
+ *  PA 7    1       0       -       -       RCLK (CLK1) for Ethernet
+ *  -------------------------------------
+ *  PA 8    1       0       -       -       TXD for COM4     (SMC2)
+ *  PA 9    1       0       -       -       RXD for COM4     (SMC2)
+ *  PA 10   0       0       -       -
+ *  PA 11   0       0       -       -
+ *  -------------------------------------
+ *  PA 12   1       0       -       -       TXD for Ethernet (SCC2)
+ *  PA 13   1       0       -       -       RXD for Ethernet (SCC2)
+ *  PA 14   0       0       -       -
+ *  PA 15   0       0       -       -
+ */
+
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD     ((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
+#define PA_ENET_TCLK    ((ushort)0x0400)	/* PA  5 */
+
+#ifndef	CONFIG_FPS850	/* not valid on FPS board */
+/*
+ * Port B:
+ *
+ * Signal   PAR     DIR     ODR     DAT     Function
+ *  ...
+ *  -------------------------------------
+ *  PB 16   0       0       -       -
+ *  PB 17   0       0       -       -
+ *  PB 18   1       1       -       -       TENA/RTS for Ethernet !!!
+ *  PB 19   0       0       -       -
+ *  -------------------------------------
+ *  ...
+ *
+ * Note: Using PC14 as RTS2 (TENA) does not work for some reason;
+ * we *must* use PB18 instead.
+ */
+#define PB_ENET_TENA	((uint)0x00002000)
+#endif	/* !CONFIG_FPS850 */
+
+/*
+ * Port C:
+ *
+ * Signal   PAR     DIR     SO      DAT     Function
+ * PC 0     0       0       0       -
+ * PC 1     0       0       0       -
+ * PC 2     0       0       0       -
+ * PC 3     0       0       0       -
+ *  -------------------------------------
+ * PC 4     0       0       0       -
+ * PC 5     0       0       0       -
+ * PC 6     0       0       0       -
+ * PC 7     0       0       0       -       -> ETH-LOOP
+ *  -------------------------------------
+ * PC 8     0       0       1       -       CD  for Ethernet (SCC2)
+ * PC 9     0       0       1       -       CTS for Ethernet (SCC2)
+ * PC 10    0       0       0       -
+ * PC 11    0       0       0       -
+ *  -------------------------------------
+ * PC 12    0       0       0       -
+ * PC 13    0       0       0       -
+ * PC 14    *       *       0       -       TENA/RTS for Ethernet
+ * PC 15    0       0       0       -
+ */
+
+#ifdef	CONFIG_FPS850		/* FPS uses default configuration */
+#define PC_ENET_TENA	((ushort)0x0002)	/* PC 14 */
+#endif	/* CONFIG_FPS850 */
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002600)
+
+#endif	/* CONFIG_TQM8xxL */
 
 #ifdef CONFIG_RPXLITE
 /* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
@@ -414,7 +578,7 @@
 
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00003d00)
-#endif
+#endif /* CONFIG_RPXLITE */
 
 #ifdef CONFIG_BSEIP
 /* This ENET stuff is for the MPC823 with ethernet on SCC2.
@@ -436,7 +600,7 @@
 
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002c00)
-#endif
+#endif /* CONFIG_BSEIP */
 
 #ifdef CONFIG_RPXCLASSIC
 /* Bits in parallel I/O port registers that have to be set/cleared
@@ -455,7 +619,8 @@
  */
 #define SICR_ENET_MASK	((uint)0x000000ff)
 #define SICR_ENET_CLKRT	((uint)0x0000003d)
-#endif
+#endif /* CONFIG_RPXCLASSIC */
+
 
 /* SCC Event register as used by Ethernet.
 */
+ diff -u linux-2.2.13/arch/ppc/8xx_io/enet.c.ORIG linux-2.2.13/arch/ppc/8xx_io/enet.c
--- linux-2.2.13/arch/ppc/8xx_io/enet.c.ORIG	Fri Oct 22 23:24:13 1999
+++ linux-2.2.13/arch/ppc/8xx_io/enet.c	Sun Jan  9 19:21:36 2000
@@ -14,13 +14,16 @@
  * Buffer descriptors are kept in the CPM dual port RAM, and the frame
  * buffers are in the host memory.
  *
- * Right now, I am very watseful with the buffers.  I allocate memory
+ * Right now, I am very wasteful with the buffers.  I allocate memory
  * pages and then divide them into 2K frame buffers.  This way I know I
  * have buffers large enough to hold one frame within one buffer descriptor.
  * Once I get this working, I will use 64 or 128 byte CPM buffers, which
  * will be much more memory efficient and will easily handle lots of
  * small packets.
  *
+ * Modifications for TQM8xx(L) modules
+ * Copyright (c) 1999,2000 Wolfgang Denk ([e-mail])
+ *
  */
 #include <linux/kernel.h>
 #include <linux/sched.h>
@@ -105,20 +108,190 @@
  *	Port B, 18 (RTS2) - Ethernet Tx Enable
  *	Port C,  8 (CD2) - Ethernet Rx Enable
  *	Port C,  9 (CTS2) - SCC Ethernet Collision
+ *
+ * For the TQM8xx(L) modules, there is no control register interface.
+ * All functions are directly controlled using I/O pins.
+ * Here is the needed port configuration (see also: "commproc.h"):
+ *
+ * TQM860 and TQM860L Configuration:
+ *
+ * Port A: 
+ *
+ * Signal   PAR     DIR     ODR     DAT     Function
+ *  PA 0    0       1       -       -       -> SENSRST 
+ *  PA 1    0       0       -       -       <- BENDE
+ *  PA 2    0       1       -       -       -> STREPP
+ *  PA 3    0       1       -       -       -> LED1 
+ *  -------------------------------------
+ *  PA 4    0       1       -       -       -> LED2 
+ *  PA 5    1       0       -       -       TCLK (CLK3) for Ethernet
+ *  PA 6    0       0       -       -          (not used)
+ *  PA 7    1       0       -       -       RCLK (CLK1) for Ethernet
+ *  -------------------------------------
+ *  PA 8    0       0       -       -       <- SWITCH1 
+ *  PA 9    0       1       -       -       -> CONF_DCK
+ *  PA 10   0       1       -       -       -> COM_SEL 
+ *  PA 11   0       0       -       -          (not used)
+ *  -------------------------------------
+ *  PA 12   1       0       -       -       TXD for Com 2    (SCC2)  
+ *  PA 13   1       0       -       -       RXD for Com 2    (SCC2)  
+ *  PA 14   1       0       -       -       TXD for Ethernet (SCC1)
+ *  PA 15   1       0       -       -       RXD for Ethernet (SCC1)
+ *
+ * Port B:
+ *
+ * Signal   PAR     DIR     ODR     DAT     Function
+ *  PB 0    0       0       -       -
+ *  PB 1    0       0       -       -
+ *  PB 2    0       0       -       -
+ *  PB 3    0       0       -       -
+ *  -------------------------------------   
+ *  PB 4    0       0       -       -          
+ *  PB 5    0       0       -       -          
+ *  PB 6    0       0       -       -          
+ *  PB 7    0       0       -       -          
+ *  -------------------------------------
+ *  PB 8    0       0       -       -       
+ *  PB 9    0       0       -       -
+ *  PB 10   0       0       -       -
+ *  PB 11   0       0       -       -
+ *  -------------------------------------
+ *  PB 12   0       0       -       -
+ *  PB 13   0       0       -       -
+ *  PB 14   0       0       -       -
+ *  PB 15   0       0       -       -
+ *  -------------------------------------
+ *  PB 16   0       0       -       -
+ *  PB 17   0       0       -       -
+ *  PB 18   0       0       -       -
+ *  PB 19   0       0       -       -
+ *  -------------------------------------
+ *  PB 20   0       0       -       -
+ *  PB 21   0       0       -       -
+ *  PB 22   0       0       -       -
+ *  PB 23   0       0       -       -
+ *  -------------------------------------
+ *  PB 24   1       0       -       -       RXD for SMC1
+ *  PB 25   1       0       -       -       TXD for SMC1
+ *  PB 26   0       0       -       -
+ *  PB 27   0       0       -       -
+ *  -------------------------------------
+ *  PB 28   0       0       -       -
+ *  PB 29   0       0       -       -
+ *  PB 30   0       0       -       -
+ *  PB 31   0       0       -       -
+ *
+ * Port C:
+ *
+ * Signal   PAR     DIR     SO      DAT     Function
+ * PC 0     0       0       0       -          (not usable)
+ * PC 1     0       0       0       -          (not usable)
+ * PC 2     0       0       0       -          (not usable)
+ * PC 3     0       0       0       -          (not usable)
+ *  -------------------------------------
+ * PC 4     0       1       0       -       -> CONF_DON (LED on old board)
+ * PC 5     0       0       0       -       <- INIT_DONE
+ * PC 6     0       0       0       -       <- CNFSTAT
+ * PC 7     0       0       0       -       -> ETH-LOOP
+ *  -------------------------------------
+ * PC 8     0       0       1       -       CD  for COM2     (SCC2)
+ * PC 9     0       0       1       -       CTS for COM2     (SCC2)
+ * PC 10    0       0       1       -       CD  for Ethernet (SCC1)
+ * PC 11    0       0       1       -       CTS for Ethernet (SCC1)
+ *  -------------------------------------
+ * PC 12    0       0       0       -       -> FPGA_OE
+ * PC 13    0       0       0       -       -> FPGA_CLR
+ * PC 14    0       0       0       -          (not used)
+ * PC 15    *       *       0       -       TENA/RTS for Ethernet
+ *
+ *
+ * TQM8xxL Configuration (except TQM860L):
+ *
+ * Port A:
+ *
+ * Signal   PAR     DIR     ODR     DAT     Function
+ *  PA 0    0       0       -       -
+ *  PA 1    0       0       -       -
+ *  PA 2    0       0       -       -
+ *  PA 3    0       0       -       -
+ *  -------------------------------------
+ *  PA 4    0       0       -       -
+ *  PA 5    1       0       -       -       TCLK (CLK3) for Ethernet
+ *  PA 6    0       0       -       -
+ *  PA 7    1       0       -       -       RCLK (CLK1) for Ethernet
+ *  -------------------------------------
+ *  PA 8    1       0       -       -       TXD for COM4     (SMC2)
+ *  PA 9    1       0       -       -       RXD for COM4     (SMC2)
+ *  PA 10   0       0       -       -
+ *  PA 11   0       0       -       -
+ *  -------------------------------------
+ *  PA 12   1       0       -       -       TXD for Ethernet (SCC2)
+ *  PA 13   1       0       -       -       RXD for Ethernet (SCC2)
+ *  PA 14   0       0       -       -
+ *  PA 15   0       0       -       -
+ *
+ * Port B:
+ *
+ * Signal   PAR     DIR     ODR     DAT     Function
+ *  ...
+ *  -------------------------------------
+ *  PB 16   0       0       -       -
+ *  PB 17   0       0       -       -
+ *  PB 18   1       1       -       -       TENA/RTS for Ethernet on starter-kit
+ *  PB 19   0       0       -       -
+ *  -------------------------------------
+ *  ...
+ *
+ * Port C:
+ *
+ * Signal   PAR     DIR     SO      DAT     Function
+ * PC 0     0       0       0       -
+ * PC 1     0       0       0       -
+ * PC 2     0       0       0       -
+ * PC 3     0       0       0       -
+ *  -------------------------------------
+ * PC 4     0       0       0       -
+ * PC 5     0       0       0       -
+ * PC 6     0       0       0       -