crc.v

此源代码实现了CRC5和CRC16的校验以及校验码的产生

/* CRC type */
`timescale 1ns/1ps
`define CRC_UNKNOWN      2'b00
`define CRC5             2'b01
`define CRC16            2'b10
`define NO_CRC           2'b11



module crc (rst, clk, decode_data_in, data_in_bit_en , data_in_frame_en ,  rsp_data_in , 
isT2R , crc_type , BLF_reverse , rsp_data_in_en ,crc16_judge ,crc5_judge, 
crc_data_out , crc_data_out_en );
  
  input            rst;
  input            clk;
  input            decode_data_in , rsp_data_in;
  input            data_in_bit_en;
  input            data_in_frame_en;  
  input            isT2R;   /* when '0'judge if "decode_data_in"  is correct, '1' produce crc of
                "rsp_data_in" and gives them to encoder, also indicates encode of preamble is over */
  input  [1:0]     crc_type; //from  center controller
  input  [5:0]     BLF_reverse;  // from encoding module          
  input            rsp_data_in_en; /*from center controller,
                                       "0" when the sending of encoding data is over*/
 // output  reg           crc_judge_result;    
  output  reg              crc16_judge;
  output  reg              crc5_judge; //"1" then decode_data_in is correct           
  output  reg           crc_data_out;
  output  reg           crc_data_out_en;    // to encoding module ,a cmd is over
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         
  reg    [15:0]    crc16_reg;    //  CRC register
  reg    [4:0 ]    crc5_reg;
  reg    [4:0]     data_out_counter;
  reg    [1:0]     data_in_bit_en_counter;      
  reg    [5:0]     BLF_reverse_count; 
  reg              crc5_en;
  reg              crc16_en;
  reg              EOF_en; 

    

always@(posedge clk or negedge rst) begin  /*because "data_in_bit_en" lasts two clocks, 
                                     so need "data_in_bit_en_counter" help to enable*/
    if(!rst) 
      data_in_bit_en_counter <= 0;
    else if(data_in_bit_en && data_in_bit_en_counter == 0)  
      data_in_bit_en_counter <= 2;
    else if (data_in_bit_en && data_in_bit_en_counter > 0)
      data_in_bit_en_counter<= data_in_bit_en_counter-1;       
    else  
      data_in_bit_en_counter <= 0;  
end 

/*always@(posedge clk or posedge rst)begin//Only one always block may assign variable crc_judge_result
    if(rst)
      crc_judge_result <= 0;
    else  
      crc_judge_result <= crc16_judge || crc5_judge ;
    end */   
         
task crc16_calculate;
  input data_in ;
  begin
  	 crc16_reg[0] <= crc16_reg[15] ^ data_in;
	 crc16_reg[1] <= crc16_reg[0];
	 crc16_reg[2] <= crc16_reg[1];
	 crc16_reg[3] <= crc16_reg[2];
	 crc16_reg[4] <= crc16_reg[3];
	 crc16_reg[5] <= crc16_reg[4] ^ ( crc16_reg[15] ^ data_in );
	 crc16_reg[6] <= crc16_reg[5];
	 crc16_reg[7] <= crc16_reg[6];
	 crc16_reg[8] <= crc16_reg[7];
	 crc16_reg[9] <= crc16_reg[8];
	 crc16_reg[10]<= crc16_reg[9];
	 crc16_reg[11]<= crc16_reg[10];
	 crc16_reg[12]<= crc16_reg[11] ^ ( crc16_reg[15] ^ data_in );
	 crc16_reg[13]<= crc16_reg[12];
	 crc16_reg[14]<= crc16_reg[13];
	 crc16_reg[15]<= crc16_reg[14];	   
  end
endtask 

task  crc16_result_judge;
   begin
     if(crc_type == `CRC16 && crc16_reg == 16'h1D0F)       
          crc16_judge<=1;   
	 end  	   
endtask

task  crc5_result_judge;
   begin
     if(crc_type == `CRC5 && crc5_reg == 5'b00000)
          crc5_judge<=1;     
	 end  	   
endtask

     
always@(posedge clk or negedge rst)  begin //crc16
    if(!rst) begin 
		   
		crc16_reg<=16'hffff; //  CRC register initializtion 
		EOF_en <=0 ;
		data_out_counter<=16;
 	    BLF_reverse_count <= 0;
 	    crc16_judge <= 0;
 		crc_data_out_en<=0;
 		crc16_en<=0;
 		crc_data_out<=0;
	 end
	
	
/* ------------crc judge of "decode_data_in"  (CRC16)----------- */	
	
else if( !isT2R && (crc_type == `CRC16 ||crc_type == `CRC_UNKNOWN))begin	 
    if(data_in_frame_en) begin  //when data_in_frame_en==1, a frame is begin
		  crc_data_out<=0;  
		  crc_data_out_en<=0; 
		  crc16_judge <= 0; 
		  BLF_reverse_count <= 0;
		  EOF_en <=0 ;
		if(data_in_bit_en && !data_in_bit_en_counter)begin // a bit is available
		 	crc16_en<=1;
 	      crc16_calculate(decode_data_in); //task
		end 
	 end  	
	 else if(!data_in_frame_en && crc16_en)begin  //crc judge of a frame is over,pruduce the result
        crc16_result_judge ;//task
        crc16_en<=0;
        crc16_reg <= 16'hffff;
    end    
end
     
else if(!isT2R && (crc_type == `NO_CRC || crc_type == `CRC5)) begin	//some cmds don't need crc judge
     crc16_en<=0;
	  crc16_reg <= 16'hffff;
end     


/* -------produce crc of "rsp_data_in" and gives them to encoder----------- */	

else  if(isT2R) begin// isT2R=1 when encode of preamble is over 
 
if(rsp_data_in_en) begin //rsp_data_in is not over      
    if(BLF_reverse_count == 0)begin  
	    BLF_reverse_count <= BLF_reverse -1 ;    
		 crc_data_out <= rsp_data_in ; //send rsp_data_in 
		 if( crc_type == `CRC16 )  begin //produce crc of "rsp_data_in"
		   crc16_en <= 1;
			crc16_calculate(rsp_data_in); //task
		 end  
		 else  ; //crc_type == `NO_CRC ,some cmds don't need crc
	  end  
	  else  if( BLF_reverse_count != 0 )
		 BLF_reverse_count <= BLF_reverse_count - 1 ;
end
else  if(!rsp_data_in_en && crc_type == `CRC16) begin //rsp_data_in is over
 
	  if(BLF_reverse_count == 0 && data_out_counter != 0 && !EOF_en)begin
		 crc_data_out <= ~crc16_reg[15] ; //send the crc_reg behind the data 
		 crc16_reg <= crc16_reg << 1;
		 BLF_reverse_count <= BLF_reverse -1 ; 
		 data_out_counter <= data_out_counter - 1; 
		end
			
      else  if(BLF_reverse_count != 0)
		 BLF_reverse_count <= BLF_reverse_count - 1 ;				    
				  	
		else if(data_out_counter == 0 && BLF_reverse_count == 0 && !EOF_en) 	begin 
		 crc_data_out <= 1 ; //send EOF
		 EOF_en <=1 ;
		 data_out_counter <= 16;
		 crc16_en <= 0;
		 crc16_reg <= 16'hffff;                      
		end
      else if(EOF_en) begin	//over
  	    crc_data_out_en <= 1; 
	    BLF_reverse_count <= 0 ;
	   end
end 
			
else  if(!rsp_data_in_en && crc_type == `NO_CRC ) begin/* need not output crc behind the data,
                                                    send EOF directly*/
      if(!EOF_en && BLF_reverse_count == 0 ) begin
	    crc_data_out <= 1 ; // send EOF
	    EOF_en <=1 ;
	   end 
	          
	   else  if( BLF_reverse_count != 0 )
		 BLF_reverse_count <= BLF_reverse_count - 1 ;  
		       
	   else if(EOF_en) begin //over
	    crc_data_out_en <= 1; 
	    BLF_reverse_count <= 0 ;
	   end
end
end
end //  always@(posedge clk or posedge rst) 


/* ------------crc judge of "decode_data_in"  is correct (CRC5)----------- */	  
	  
always@(posedge clk or negedge rst)   //crc 5
if(!rst) begin
   crc5_en<=0;
	crc5_judge <= 0;
	crc5_reg<=5'b01001;
end	
	
else begin
   if(data_in_frame_en) begin  //when data_in_frame_en==1, a frame is begin
       crc5_judge <= 0;
		 if(!isT2R && (crc_type == `CRC5 ||  crc_type == `CRC_UNKNOWN))begin
		    if(data_in_bit_en && data_in_bit_en_counter == 0)begin// a bit is available
		    		   crc5_en<=1;
				   crc5_reg[0]<=crc5_reg[4]^decode_data_in;
				   crc5_reg[1]<=crc5_reg[0];
				   crc5_reg[2]<=crc5_reg[1];
				   crc5_reg[3]<=crc5_reg[2]^(crc5_reg[4]^decode_data_in);
				   crc5_reg[4]<=crc5_reg[3];
			 end
		  end	 
		  else begin//ont if(!isT2R && (crc_type == `CRC5 ||  crc_type == `CRC_UNKNOWN))
		       	 crc5_reg<=5'b01001;
		         crc5_en<=0;
	            crc5_judge <= 0;
		  end 
	end
	else if(!data_in_frame_en && crc5_en)  //crc checkout is over
	     if(!isT2R && (crc_type == `CRC5 || crc_type == `CRC_UNKNOWN))begin  		    
		  crc5_result_judge ;  //task
        crc5_reg <= 5'b01001;
        crc5_en<=0;
		  end

 end  // crc5
	  
endmodule