hipe_arm_encode.erl

来自「OTP是开放电信平台的简称」· ERL 代码 · 共 978 行 · 第 1/3 页

    'teq' -> teq(Opnds);
    'tst' -> tst(Opnds);
    'umlal' -> umlal(Opnds);
    'umull' -> umull(Opnds);
    _ -> exit({?MODULE,insn_encode,Op})
  end.

%%%
%%% Testing Interface
%%%

-ifdef(TESTING).

say(OS, Str) ->
  file:write(OS, Str).

hex_digit(Dig0) ->
  Dig = Dig0 band 16#F,
  if Dig >= 16#A -> $A + (Dig - 16#A);
     true -> $0 + Dig
  end.

say_byte(OS, Byte) ->
  say(OS, [hex_digit(Byte bsr 4)]),
  say(OS, [hex_digit(Byte)]).

say_word(OS, Word) ->
  say(OS, "0x"),
  say_byte(OS, Word bsr 24),
  say_byte(OS, Word bsr 16),
  say_byte(OS, Word bsr 8),
  say_byte(OS, Word).

t(OS, Op, Opnds) ->
  Word = insn_encode(Op, Opnds),
  say(OS, "\t.long "),
  say_word(OS, Word),
  say(OS, "\n").

dotest1(OS) ->
  say(OS, "\t.text\n\t.align 4\n"),
  %%
  Rn = {r,9},
  Rd = {r,8},	% must be even and less than 14 for some insns
  Rm = {r,7},
  Rs = {r,6},
  RdLo = Rn,
  RdHi = Rd,
  Registers = [Rm,Rs,Rd],	% must exclude Rn for some insns
  CRd = {cr,15},
  CRn = {cr,14},
  CRm = {cr,13},
  BT0 = {bt,0},
  BT1 = {bt,1},
  CpNum = {cpnum,15},
  CpOp3 = {cpop3,16#3},
  CpOp4 = {cpop4,16#F},
  L0 = {l,0},
  L1 = {l,1},
  S0 = {s,0},
  S1 = {s,1},
  FieldMask4 = {field_mask,16#F},
  Imm4 = {imm4,16#F},
  Imm5 = {imm5,16#1F},
  Imm8 = {imm8,16#FF},
  Imm12 = {imm12,16#FFF},
  Imm16 = {imm16,16#FFFF},
  Imm24 = {imm24,16#FFFFF},
  Imm25 = {imm25,16#FFFFF1},
  %%
  AM1_1 = {Imm8,Imm4},
  AM1_2 = Rm,
  AM1_3_1 = {Rm,{'lsl',Imm5}},
  AM1_3_2 = {Rm,{'lsr',Imm5}},
  AM1_3_3 = {Rm,{'asr',Imm5}},
  AM1_3_4 = {Rm,{'ror',Imm5}},
  AM1_3_5 = {Rm,{'lsl',Rs}},
  AM1_3_6 = {Rm,{'lsr',Rs}},
  AM1_3_7 = {Rm,{'asr',Rs}},
  AM1_3_8 = {Rm,{'ror',Rs}},
  AM1_3_9 = {Rm,'rrx'},
  %%
  AM2ShiftOp1 = {'lsl',Imm5},
  AM2ShiftOp2 = {'lsr',Imm5},
  AM2ShiftOp3 = {'asr',Imm5},
  AM2ShiftOp4 = {'ror',Imm5},
  AM2ShiftOp5 = 'rrx',
  SignP = '+',
  SignM = '-',
  AM2_1_1 = {immediate_offset,Rn,SignP,Imm12},
  AM2_1_2 = {immediate_offset,Rn,SignM,Imm12},
  AM2_2_1 = {register_offset,Rn,SignP,Rm},
  AM2_2_2 = {register_offset,Rn,SignM,Rm},
  AM2_3_1 = {scaled_register_offset,Rn,SignP,Rm,AM2ShiftOp1},
  AM2_3_2 = {scaled_register_offset,Rn,SignM,Rm,AM2ShiftOp2},
  AM2_3_3 = {scaled_register_offset,Rn,SignP,Rm,AM2ShiftOp3},
  AM2_3_4 = {scaled_register_offset,Rn,SignM,Rm,AM2ShiftOp4},
  AM2_3_5 = {scaled_register_offset,Rn,SignP,Rm,AM2ShiftOp5},
  AM2_4_1 = {immediate_pre_indexed,Rn,SignP,Imm12},
  AM2_4_2 = {immediate_pre_indexed,Rn,SignM,Imm12},
  AM2_5_1 = {register_pre_indexed,Rn,SignP,Rm},
  AM2_5_2 = {register_pre_indexed,Rn,SignM,Rm},
  AM2_6_1 = {scaled_register_pre_indexed,Rn,SignP,Rm,AM2ShiftOp1},
  AM2_6_2 = {scaled_register_pre_indexed,Rn,SignM,Rm,AM2ShiftOp2},
  AM2_6_3 = {scaled_register_pre_indexed,Rn,SignP,Rm,AM2ShiftOp3},
  AM2_6_4 = {scaled_register_pre_indexed,Rn,SignM,Rm,AM2ShiftOp4},
  AM2_6_5 = {scaled_register_pre_indexed,Rn,SignP,Rm,AM2ShiftOp5},
  AM2_7_1 = {immediate_post_indexed,Rn,SignP,Imm12},
  AM2_7_2 = {immediate_post_indexed,Rn,SignM,Imm12},
  AM2_8_1 = {register_post_indexed,Rn,SignP,Rm},
  AM2_8_2 = {register_post_indexed,Rn,SignM,Rm},
  AM2_9_1 = {scaled_register_post_indexed,Rn,SignP,Rm,AM2ShiftOp1},
  AM2_9_2 = {scaled_register_post_indexed,Rn,SignM,Rm,AM2ShiftOp2},
  AM2_9_3 = {scaled_register_post_indexed,Rn,SignP,Rm,AM2ShiftOp3},
  AM2_9_4 = {scaled_register_post_indexed,Rn,SignM,Rm,AM2ShiftOp4},
  AM2_9_5 = {scaled_register_post_indexed,Rn,SignP,Rm,AM2ShiftOp5},
  %%
  AM3_1_1 = {immediate_offset,Rn,SignP,Imm8},
  AM3_1_2 = {immediate_offset,Rn,SignM,Imm8},
  AM3_2_1 = {register_offset,Rn,SignP,Rm},
  AM3_2_2 = {register_offset,Rn,SignM,Rm},
  AM3_3_1 = {immediate_pre_indexed,Rn,SignP,Imm8},
  AM3_3_2 = {immediate_pre_indexed,Rn,SignM,Imm8},
  AM3_4_1 = {register_pre_indexed,Rn,SignP,Rm},
  AM3_4_2 = {register_pre_indexed,Rn,SignM,Rm},
  AM3_5_1 = {immediate_post_indexed,Rn,SignP,Imm8},
  AM3_5_2 = {immediate_post_indexed,Rn,SignM,Imm8},
  AM3_6_1 = {register_post_indexed,Rn,SignP,Rm},
  AM3_6_2 = {register_post_indexed,Rn,SignM,Rm},
  %%
  AM4_1 = 'ia',
  AM4_2 = 'ib',
  AM4_3 = 'da',
  AM4_4 = 'db',
  AM4_5 = 'fa',
  AM4_6 = 'fd',
  AM4_7 = 'ea',
  AM4_8 = 'ed',
  %%
  AM5_1_1 = {offset,Rn,SignP,Imm8},
  AM5_1_2 = {offset,Rn,SignM,Imm8},
  AM5_2_1 = {pre_indexed,Rn,SignP,Imm8},
  AM5_2_2 = {pre_indexed,Rn,SignM,Imm8},
  AM5_3_1 = {post_indexed,Rn,SignP,Imm8},
  AM5_3_2 = {post_indexed,Rn,SignM,Imm8},
  AM5_4 = {unindexed,Rn,Imm8},
  %%
  Cond_eq = {'cond','eq'},
  Cond_ne = {'cond','ne'},
  Cond_cs = {'cond','cs'},
  Cond_hs = {'cond','hs'},
  Cond_cc = {'cond','cc'},
  Cond_lo = {'cond','lo'},
  Cond_mi = {'cond','mi'},
  Cond_pl = {'cond','pl'},
  Cond_vs = {'cond','vs'},
  Cond_vc = {'cond','vc'},
  Cond_hi = {'cond','hi'},
  Cond_ls = {'cond','ls'},
  Cond_ge = {'cond','ge'},
  Cond_lt = {'cond','lt'},
  Cond_gt = {'cond','gt'},
  Cond_le = {'cond','le'},
  Cond_al = {'cond','al'},
  %%
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_1}),		% test all AM1 operands
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_2}),
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_3_1}),
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_3_2}),
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_3_3}),
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_3_4}),
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_3_5}),
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_3_6}),
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_3_7}),
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_3_8}),
  t(OS,'adc',{Cond_al,S0,Rd,Rn,AM1_3_9}),
  t(OS,'add',{Cond_al,S0,Rd,Rn,AM1_1}),		% test all S operands
  t(OS,'add',{Cond_al,S1,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_eq,S0,Rd,Rn,AM1_1}),		% test all Cond operands
  t(OS,'and',{Cond_ne,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_cs,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_hs,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_cc,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_lo,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_mi,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_pl,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_vs,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_vc,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_hi,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_ls,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_ge,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_lt,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_gt,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_le,S0,Rd,Rn,AM1_1}),
  t(OS,'and',{Cond_al,S0,Rd,Rn,AM1_1}),
  t(OS,'b',{Cond_al,Imm24}),
  t(OS,'bic',{Cond_al,S0,Rd,Rn,AM1_1}),
  t(OS,'bkpt',{Imm16}),
  t(OS,'bl',{Cond_al,Imm24}),
  t(OS,'blx',{Imm25}),
  t(OS,'blx',{Cond_al,Rm}),
  t(OS,'bx',{Cond_al,Rm}),
  t(OS,'cdp',{Cond_al,CpNum,CpOp4,CRd,CRn,CRm,CpOp3}),
  t(OS,'cdp2',{CpNum,CpOp4,CRd,CRn,CRm,CpOp3}),
  t(OS,'clz',{Cond_al,Rd,Rm}),
  t(OS,'cmn',{Cond_al,Rn,AM1_1}),
  t(OS,'cmp',{Cond_al,Rn,AM1_1}),
  t(OS,'eor',{Cond_al,S0,Rd,Rn,AM1_1}),
  t(OS,'ldc',{Cond_al,L0,CpNum,CRd,AM5_1_1}),	% test all AM5 operands
  t(OS,'ldc',{Cond_al,L1,CpNum,CRd,AM5_1_2}),
  t(OS,'ldc',{Cond_al,L0,CpNum,CRd,AM5_2_1}),
  t(OS,'ldc',{Cond_al,L1,CpNum,CRd,AM5_2_2}),
  t(OS,'ldc',{Cond_al,L0,CpNum,CRd,AM5_3_1}),
  t(OS,'ldc',{Cond_al,L1,CpNum,CRd,AM5_3_2}),
  t(OS,'ldc',{Cond_al,L0,CpNum,CRd,AM5_4}),
  t(OS,'ldc2',{L0,CpNum,CRd,AM5_1_1}),
  t(OS,'ldm',{Cond_al,AM4_1,Rn,'!',Registers}),
  t(OS,'ldm',{Cond_al,AM4_1,Rn,Registers}),	% test all AM4 operands
  t(OS,'ldm',{Cond_al,AM4_2,Rn,Registers}),	% test all AM4 operands
  t(OS,'ldm',{Cond_al,AM4_3,Rn,Registers}),	% test all AM4 operands
  t(OS,'ldm',{Cond_al,AM4_4,Rn,Registers}),	% test all AM4 operands
  t(OS,'ldm',{Cond_al,AM4_5,Rn,Registers}),	% test all AM4 operands
  t(OS,'ldm',{Cond_al,AM4_6,Rn,Registers}),	% test all AM4 operands
  t(OS,'ldm',{Cond_al,AM4_7,Rn,Registers}),	% test all AM4 operands
  t(OS,'ldm',{Cond_al,AM4_8,Rn,Registers}),	% test all AM4 operands
  t(OS,'ldr',{Cond_al,Rd,AM2_1_1}),		% test all AM2 operands
  t(OS,'ldr',{Cond_al,Rd,AM2_1_2}),
  t(OS,'ldr',{Cond_al,Rd,AM2_2_1}),
  t(OS,'ldr',{Cond_al,Rd,AM2_2_2}),
  t(OS,'ldr',{Cond_al,Rd,AM2_3_1}),
  t(OS,'ldr',{Cond_al,Rd,AM2_3_2}),
  t(OS,'ldr',{Cond_al,Rd,AM2_3_3}),
  t(OS,'ldr',{Cond_al,Rd,AM2_3_4}),
  t(OS,'ldr',{Cond_al,Rd,AM2_3_5}),
  t(OS,'ldr',{Cond_al,Rd,AM2_4_1}),
  t(OS,'ldr',{Cond_al,Rd,AM2_4_2}),
  t(OS,'ldr',{Cond_al,Rd,AM2_5_1}),
  t(OS,'ldr',{Cond_al,Rd,AM2_5_2}),
  t(OS,'ldr',{Cond_al,Rd,AM2_6_1}),
  t(OS,'ldr',{Cond_al,Rd,AM2_6_2}),
  t(OS,'ldr',{Cond_al,Rd,AM2_6_3}),
  t(OS,'ldr',{Cond_al,Rd,AM2_6_4}),
  t(OS,'ldr',{Cond_al,Rd,AM2_6_5}),
  t(OS,'ldr',{Cond_al,Rd,AM2_7_1}),
  t(OS,'ldr',{Cond_al,Rd,AM2_7_2}),
  t(OS,'ldr',{Cond_al,Rd,AM2_8_1}),
  t(OS,'ldr',{Cond_al,Rd,AM2_8_2}),
  t(OS,'ldr',{Cond_al,Rd,AM2_9_1}),
  t(OS,'ldr',{Cond_al,Rd,AM2_9_2}),
  t(OS,'ldr',{Cond_al,Rd,AM2_9_3}),
  t(OS,'ldr',{Cond_al,Rd,AM2_9_4}),
  t(OS,'ldr',{Cond_al,Rd,AM2_9_5}),
  t(OS,'ldrb',{Cond_al,Rd,AM2_1_1}),
  t(OS,'ldrd',{Cond_al,Rd,AM3_1_1}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_1_1}),	% test all AM3 operands
  t(OS,'ldrh',{Cond_al,Rd,AM3_1_2}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_2_1}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_2_2}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_3_1}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_3_2}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_4_1}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_4_2}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_5_1}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_5_2}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_6_1}),
  t(OS,'ldrh',{Cond_al,Rd,AM3_6_2}),
  t(OS,'ldrsb',{Cond_al,Rd,AM3_1_1}),
  t(OS,'ldrsh',{Cond_al,Rd,AM3_1_1}),
  t(OS,'mcr',{Cond_al,CpNum,CpOp3,Rd,CRn,CRm,CpOp3}),
  t(OS,'mcr2',{CpNum,CpOp3,Rd,CRn,CRm,CpOp3}),
  t(OS,'mcrr',{Cond_al,CpNum,CpOp4,Rd,Rn,CRm}),
  t(OS,'mla',{Cond_al,S0,Rd,Rm,Rs,Rn}),
  t(OS,'mov',{Cond_al,S0,Rd,AM1_1}),
  t(OS,'mrc',{Cond_al,CpNum,CpOp3,Rd,CRn,CRm,CpOp3}),
  t(OS,'mrc2',{CpNum,CpOp3,Rd,CRn,CRm,CpOp3}),
  t(OS,'mrrc',{Cond_al,CpNum,CpOp4,Rd,Rn,CRm}),
  t(OS,'mrs',{Cond_al,Rd,'cpsr'}),
  t(OS,'msr',{Cond_al,'cpsr',FieldMask4,Imm8,Imm4}),
  t(OS,'msr',{Cond_al,'cpsr',FieldMask4,Rm}),
  t(OS,'mul',{Cond_al,S0,Rd,Rm,Rs}),
  t(OS,'mvn',{Cond_al,S1,Rd,AM1_1}),
  t(OS,'orr',{Cond_al,S0,Rd,Rn,AM1_1}),
  t(OS,'pld',{AM2_1_1}),
  t(OS,'qadd',{Cond_al,Rd,Rm,Rn}),
  t(OS,'qdadd',{Cond_al,Rd,Rm,Rn}),
  t(OS,'qdsub',{Cond_al,Rd,Rm,Rn}),
  t(OS,'qsub',{Cond_al,Rd,Rm,Rn}),
  t(OS,'rsb',{Cond_al,S0,Rd,Rn,AM1_1}),
  t(OS,'rsc',{Cond_al,S0,Rd,Rn,AM1_1}),
  t(OS,'sbc',{Cond_al,S0,Rd,Rn,AM1_1}),
  t(OS,'smla',{BT0,BT0,Cond_al,Rd,Rm,Rs,Rn}),
  t(OS,'smla',{BT0,BT1,Cond_al,Rd,Rm,Rs,Rn}),
  t(OS,'smla',{BT1,BT0,Cond_al,Rd,Rm,Rs,Rn}),
  t(OS,'smla',{BT1,BT1,Cond_al,Rd,Rm,Rs,Rn}),
  t(OS,'smlal',{Cond_al,S0,RdLo,RdHi,Rm,Rs}),
  t(OS,'smlal',{BT0,BT1,Cond_al,RdLo,RdHi,Rm,Rs}),
  t(OS,'smlaw',{BT1,Cond_al,Rd,Rm,Rs,Rn}),
  t(OS,'smull',{Cond_al,S0,RdLo,RdHi,Rm,Rs}),
  t(OS,'smul',{BT1,BT0,Cond_al,Rd,Rm,Rs}),
  t(OS,'smulw',{BT1,Cond_al,Rd,Rm,Rs}),
  t(OS,'stc',{Cond_al,L0,CpNum,CRd,AM5_1_1}),
  t(OS,'stc2',{L0,CpNum,CRd,AM5_1_1}),
  t(OS,'stm',{Cond_al,AM4_1,Rn,Registers}),
  t(OS,'str',{Cond_al,Rd,AM2_1_1}),
  t(OS,'strb',{Cond_al,Rd,AM2_1_1}),
  t(OS,'strd',{Cond_al,Rd,AM3_1_1}),
  t(OS,'strh',{Cond_al,Rd,AM3_1_1}),
  t(OS,'sub',{Cond_al,S0,Rd,Rn,AM1_1}),
  t(OS,'swi',{Cond_al,Imm24}),
  t(OS,'swp',{Cond_al,Rd,Rm,Rn}),
  t(OS,'swpb',{Cond_al,Rd,Rm,Rn}),
  t(OS,'teq',{Cond_al,Rn,AM1_1}),
  t(OS,'tst',{Cond_al,Rn,AM1_1}),
  t(OS,'umlal',{Cond_al,S0,RdLo,RdHi,Rm,Rs}),
  t(OS,'umull',{Cond_al,S0,RdLo,RdHi,Rm,Rs}),
  [].

dotest() -> dotest1(group_leader()).

dotest(File) ->
  {ok,OS} = file:open(File, [write]),
  dotest1(OS),
  file:close(OS).

-endif.