hipe_arm_encode.erl

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  end,
  'cond'(Cond) bor ?BF(27,20,2#00010010) bor ?BF(19,16,2#1111) bor ?BF(15,12,2#1111) bor ?BF(11,8,2#1111) bor ?BF(7,4,SubOpcode) bor ?BF(3,0,Rm).

blx(Opnds) ->
  case Opnds of
    {{imm25,Imm25}} ->	% u16-offset!
      ?BF(31,28,2#1111) bor ?BF(27,25,2#101) bor ?BIT(24,Imm25 band 1) bor ?BF(23,0,Imm25 bsr 1);
    _ ->
      bx_form(2#0011, Opnds, true)
  end.

bx(Opnds) -> bx_form(2#0001, Opnds, false).

cdp_form(Cond, CpOp4, CRn, CRd, CpNum, CpOp3, CRm) ->
  Cond bor ?BF(27,24,2#1110) bor ?BF(23,20,CpOp4) bor ?BF(19,16,CRn) bor ?BF(15,12,CRd) bor ?BF(11,8,CpNum) bor ?BF(7,5,CpOp3) bor ?BF(3,0,CRm).

cdp({{'cond',Cond},{cpnum,CpNum},{cpop4,CpOp4},{cr,CRd},{cr,CRn},{cr,CRm},{cpop3,CpOp3}}) ->
  cdp_form('cond'(Cond), CpOp4, CRn, CRd, CpNum, CpOp3, CRm).

cdp2({{cpnum,CpNum},{cpop4,CpOp4},{cr,CRd},{cr,CRn},{cr,CRm},{cpop3,CpOp3}}) ->
  cdp_form(?BF(31,28,2#1111), CpOp4, CRn, CRd, CpNum, CpOp3, CRm).

clz({{'cond',Cond},{r,Rd},{r,Rm}}) ->
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rm =/= 15),	% UNPREDICTABLE
  'cond'(Cond) bor ?BF(27,20,2#00010110) bor ?BF(19,16,2#1111) bor ?BF(15,12,Rd) bor ?BF(11,8,2#1111) bor ?BF(7,4,2#0001) bor ?BF(3,0,Rm).

ldstc_form(Cond, L, B20, CRd, CpNum, AddressingMode) ->
  Cond bor ?BF(27,25,2#110) bor ?BIT(22,L) bor ?BIT(20,B20) bor ?BF(15,12,CRd) bor ?BF(11,8,CpNum) bor am5_ls_coprocessor(AddressingMode).

ldstc(B20, {{'cond',Cond},{l,L},{cpnum,CpNum},{cr,CRd},AddressingMode}) ->
  ldstc_form('cond'(Cond), L, B20, CRd, CpNum, AddressingMode).

ldc(Opnds) -> ldstc(1, Opnds).
stc(Opnds) -> ldstc(0, Opnds).

ldstc2(B20, {{l,L},{cpnum,CpNum},{cr,CRd},AddressingMode}) ->
  ldstc_form(?BF(31,28,2#1111), L, B20, CRd, CpNum, AddressingMode).

ldc2(Opnds) -> ldstc2(1, Opnds).
stc2(Opnds) -> ldstc2(0, Opnds).

ldstm_form(Cond, AddressingMode, W, L, Rn, Registers) ->
  RegisterList = register_list(Registers),
  ?ASSERT(RegisterList =/= 0),	% UNPREDICTABLE
  ?ASSERT(Rn =/= 15),		% UNPREDICTABLE
  case W of
    1 ->
      BitRn = 1 bsl Rn,
      case L of
	1 ->
	  %% LDM! Rn in Registers is UNPREDICTABLE
	  ?ASSERT((RegisterList band BitRn) =:= 0);
	0 ->
	  %% STM! Rn in Registers and not lowest is UNPREDICTABLE
	  case RegisterList band BitRn of
	    0 -> [];
	    _ ->
	      ?ASSERT((RegisterList band (-RegisterList)) =:= BitRn)
	  end
      end;
    _ -> []
  end,
  'cond'(Cond) bor ?BF(27,25,2#100) bor am4_ls_multiple(L, AddressingMode) bor ?BIT(21,W) bor ?BIT(20,L) bor ?BF(19,16,Rn) bor ?BF(15,0,RegisterList).

register_list(Registers) -> register_list(Registers, 0).

register_list([{r,R}|Rs], Mask) -> register_list(Rs, Mask bor (1 bsl R));
register_list([], Mask) -> Mask.

ldstm(L, Opnds) ->
  case Opnds of
    {{'cond',Cond},AddressingMode,{r,Rn},'!',Registers} ->
      ldstm_form(Cond, AddressingMode, 1, L, Rn, Registers);
    {{'cond',Cond},AddressingMode,{r,Rn},Registers} ->
      ldstm_form(Cond, AddressingMode, 0, L, Rn, Registers)
    %% the ldm(2), ldm(3), and stm(2) forms are UNPREDICTABLE
    %% in User or System mode
  end.

ldm(Opnds) -> ldstm(1, Opnds).
stm(Opnds) -> ldstm(0, Opnds).

ldstr_form2(B, L, {{'cond',Cond},{r,Rd},AddressingMode}) ->
  'cond'(Cond) bor ?BF(27,26,2#01) bor am2_lswub(Rd, AddressingMode) bor ?BIT(22,B) bor ?BIT(20,L) bor ?BF(15,12,Rd).

ldr(Opnds) -> ldstr_form2(0, 1, Opnds).
ldrb(Opnds) -> ldstr_form2(1, 1, Opnds).
str(Opnds) -> ldstr_form2(0, 0, Opnds).
strb(Opnds) -> ldstr_form2(1, 0, Opnds).

ldstr_form3(L, SubOpcode, {{'cond',Cond},{r,Rd},AddressingMode}) ->
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  'cond'(Cond) bor am3_miscls(Rd, AddressingMode) bor ?BIT(20,L) bor ?BF(15,12,Rd) bor ?BF(7,4,SubOpcode).

ldrh(Opnds) -> ldstr_form3(1, 2#1011, Opnds).
ldrsb(Opnds) -> ldstr_form3(1, 2#1101, Opnds).
ldrsh(Opnds) -> ldstr_form3(1, 2#1111, Opnds).
strh(Opnds) -> ldstr_form3(0, 2#1011, Opnds).

mcr_form(Cond, OP1, CRn, Rd, CpNum, OP2, CRm) ->
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  Cond bor ?BF(27,24,2#1110) bor ?BF(23,21,OP1) bor ?BF(19,16,CRn) bor ?BF(15,12,Rd) bor ?BF(11,8,CpNum) bor ?BF(7,5,OP2) bor ?BIT(4,1) bor ?BF(3,0,CRm).

mcr({{'cond',Cond},{cpnum,CpNum},{cpop3,OP1},{r,Rd},{cr,CRn},{cr,CRm},{cpop3,OP2}}) ->
  mcr_form('cond'(Cond), OP1, CRn, Rd, CpNum, OP2, CRm).

mcr2({{cpnum,CpNum},{cpop3,OP1},{r,Rd},{cr,CRn},{cr,CRm},{cpop3,OP2}}) ->
  mcr_form(?BF(31,28,2#1111), OP1, CRn, Rd, CpNum, OP2, CRm).

mla({{'cond',Cond},{s,S},{r,Rd},{r,Rm},{r,Rs},{r,Rn}}) ->
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rm =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rs =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rn =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rd =/= Rm),	% UNPREDICTABLE
  'cond'(Cond) bor ?BIT(21,1) bor ?BIT(20,S) bor ?BF(19,16,Rd) bor ?BF(15,12,Rn) bor ?BF(11,8,Rs) bor ?BF(7,4,2#1001) bor ?BF(3,0,Rm).

mrc_form(Cond, OP1, CRn, Rd, CpNum, OP2, CRm) ->
  Cond bor ?BF(27,24,2#1110) bor ?BF(23,21,OP1) bor ?BIT(20,1) bor ?BF(19,16,CRn) bor ?BF(15,12,Rd) bor ?BF(11,8,CpNum) bor ?BF(7,5,OP2) bor ?BIT(4,1) bor ?BF(3,0,CRm).

mrc({{'cond',Cond},{cpnum,CpNum},{cpop3,OP1},{r,Rd},{cr,CRn},{cr,CRm},{cpop3,OP2}}) ->
  mrc_form('cond'(Cond), OP1, CRn, Rd, CpNum, OP2, CRm).

mrc2({{cpnum,CpNum},{cpop3,OP1},{r,Rd},{cr,CRn},{cr,CRm},{cpop3,OP2}}) ->
  mrc_form(?BF(31,28,2#1111), OP1, CRn, Rd, CpNum, OP2, CRm).

mrs({{'cond',Cond},{r,Rd},'cpsr'}) ->
  %% the SPSR form is UNPREDICTABLE in User or System mode
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  'cond'(Cond) bor ?BIT(24,1) bor ?BF(19,16,2#1111) bor ?BF(15,12,Rd).

msr_form(Cond, FieldMask4, Operand) ->
  'cond'(Cond) bor ?BIT(24,1) bor ?BIT(21,1) bor ?BF(19,16,FieldMask4) bor ?BF(15,12,2#1111) bor Operand.

msr(Opnds) ->
  %% the SPSR form is UNPREDICTABLE in User or System mode
  case Opnds of
    {{'cond',Cond},'cpsr',{field_mask,FieldMask4},{imm8,Imm8},{imm4,RotImm4}} ->
      msr_form(Cond, FieldMask4, ?BIT(25,1) bor ?BF(11,8,RotImm4) bor ?BF(7,0,Imm8));
    {{'cond',Cond},'cpsr',{field_mask,FieldMask4},{r,Rm}} ->
      msr_form(Cond, FieldMask4, ?BF(3,0,Rm))
  end.

mul({{'cond',Cond},{s,S},{r,Rd},{r,Rm},{r,Rs}}) ->
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rm =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rs =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rd =/= Rm),	% UNPREDICTABLE
  'cond'(Cond) bor ?BIT(20,S) bor ?BF(19,16,Rd) bor ?BF(11,8,Rs) bor ?BF(7,4,2#1001) bor ?BF(3,0,Rm).

ml_form2(OpCode, Cond, S, RdLo, RdHi, Rm, Rs) ->
  ?ASSERT(RdHi =/= 15),	% UNPREDICTABLE
  ?ASSERT(RdLo =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rm =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rs =/= 15),	% UNPREDICTABLE
  ?ASSERT(RdHi =/= RdLo),% UNPREDICTABLE
  ?ASSERT(RdHi =/= Rm),	% UNPREDICTABLE
  ?ASSERT(RdLo =/= Rm),	% UNPREDICTABLE
  'cond'(Cond) bor ?BF(27,21,OpCode) bor ?BIT(20,S) bor ?BF(19,16,RdHi) bor ?BF(15,12,RdLo) bor ?BF(11,8,Rs) bor ?BF(7,4,2#1001) bor ?BF(3,0,Rm).

ml_form(OpCode, {{'cond',Cond},{s,S},{r,RdLo},{r,RdHi},{r,Rm},{r,Rs}}) ->
  ml_form2(OpCode, Cond, S, RdLo, RdHi, Rm, Rs).

%%smlal(Opnds) -> ml_form(2#0000111, Opnds).
smull(Opnds) -> ml_form(2#0000110, Opnds).
umlal(Opnds) -> ml_form(2#0000101, Opnds).
umull(Opnds) -> ml_form(2#0000100, Opnds).

swi({{'cond',Cond},{imm24,Imm24}}) ->
  'cond'(Cond) bor ?BF(27,24,2#1111) bor ?BF(23,0,Imm24).

swp_form(B22, {{'cond',Cond},{r,Rd},{r,Rm},{r,Rn}}) ->
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rm =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rn =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rn =/= Rm),	% UNPREDICTABLE
  ?ASSERT(Rn =/= Rd),	% UNPREDICTABLE
  'cond'(Cond) bor ?BIT(24,1) bor ?BIT(22,B22) bor ?BF(19,16,Rn) bor ?BF(15,12,Rd) bor ?BF(7,4,2#1001) bor ?BF(3,0,Rm).

swp(Opnds) -> swp_form(0, Opnds).
swpb(Opnds) -> swp_form(1, Opnds).

%%%
%%% Enhanced DSP Extension Instructions
%%%

ldstrd_form(OpCode, {{'cond',Cond},{r,Rd},AddressingMode}) ->
  ?ASSERT(Rd =/= 14),		% UNPREDICTABLE
  ?ASSERT((Rd band 1) =:= 0),	% UNDEFINED
  %% XXX: unpredictable if write-back and base reg Rn equals Rd or Rd+1
  %% XXX: if is load then unpredictable if index reg Rm and Rm equals Rd or Rd+1
  'cond'(Cond) bor am3_miscls(Rd, AddressingMode) bor ?BF(15,12,Rd) bor ?BF(7,4,OpCode).

ldrd(Opnds) -> ldstrd_form(2#1101, Opnds).
strd(Opnds) -> ldstrd_form(2#1111, Opnds).

mcrr({{'cond',Cond},{cpnum,CpNum},{cpop4,OP},{r,Rd},{r,Rn},{cr,CRm}}) ->
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rn =/= 15),	% UNPREDICTABLE
  'cond'(Cond) bor ?BF(27,20,2#11000100) bor ?BF(19,16,Rn) bor ?BF(15,12,Rd) bor ?BF(11,8,CpNum) bor ?BF(7,4,OP) bor ?BF(3,0,CRm).

mrrc({{'cond',Cond},{cpnum,CpNum},{cpop4,OP},{r,Rd},{r,Rn},{cr,CRm}}) ->
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rn =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rd =/= Rn),	% UNPREDICTABLE
  'cond'(Cond) bor ?BF(27,20,2#11000101) bor ?BF(19,16,Rn) bor ?BF(15,12,Rd) bor ?BF(11,8,CpNum) bor ?BF(7,4,OP) bor ?BF(3,0,CRm).

pld({AddressingMode}) ->
  AM = am2_lswub(42, AddressingMode), % 42 is a dummy reg nr
  %% not all adressing modes are allowed: bit 24 must be 1
  %% and bit 21 must be 0
  ?ASSERT(((AM bsr 21) band 2#1001) =:= 2#1000),
  16#F550F000 bor AM.

q_form(OpCode, {{'cond',Cond},{r,Rd},{r,Rm},{r,Rn}}) ->
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rm =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rn =/= 15),	% UNPREDICTABLE
  'cond'(Cond) bor ?BF(27,20,OpCode) bor ?BF(19,16,Rn) bor ?BF(15,11,Rd) bor ?BF(7,4,2#0101) bor ?BF(3,0,Rm).

qadd(Opnds) -> q_form(2#00010000, Opnds).
qdadd(Opnds) -> q_form(2#00010100, Opnds).
qdsub(Opnds) -> q_form(2#00010110, Opnds).
qsub(Opnds) -> q_form(2#00010010, Opnds).

smlaxy_form(Cond, OpCode, Rd, Rn, Rs, Y, X, Rm) ->
  ?ASSERT(Rd =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rm =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rs =/= 15),	% UNPREDICTABLE
  ?ASSERT(Rn =/= 15),	% UNPREDICTABLE
  'cond'(Cond) bor ?BF(27,20,OpCode) bor ?BF(19,16,Rd) bor ?BF(15,12,Rn) bor ?BF(11,8,Rs) bor ?BIT(7,1) bor ?BIT(6,Y) bor ?BIT(5,X) bor ?BF(3,0,Rm).

smla({{bt,X},{bt,Y},{'cond',Cond},{r,Rd},{r,Rm},{r,Rs},{r,Rn}}) ->
  smlaxy_form(Cond, 2#00010000, Rd, Rn, Rs, Y, X, Rm).

smlal(Opnds) -> % may be regular ARM or DSP insn :-(
  case Opnds of
    {{'cond',Cond},{s,S},{r,RdLo},{r,RdHi},{r,Rm},{r,Rs}} ->
      ml_form2(2#0000111, Cond, S, RdLo, RdHi, Rm, Rs);
    {{bt,X},{bt,Y},{'cond',Cond},{r,RdLo},{r,RdHi},{r,Rm},{r,Rs}} ->
      ?ASSERT(RdLo =/= RdHi),	% UNPREDICTABLE
      smlaxy_form(Cond, 2#00010100, RdHi, RdLo, Rs, Y, X, Rm)
  end.

smlaw({{bt,Y},{'cond',Cond},{r,Rd},{r,Rm},{r,Rs},{r,Rn}}) ->
  smlaxy_form(Cond, 2#00010010, Rd, Rn, Rs, Y, 0, Rm).
  
smul({{bt,X},{bt,Y},{'cond',Cond},{r,Rd},{r,Rm},{r,Rs}}) ->
  smlaxy_form(Cond, 2#00010110, Rd, 0, Rs, Y, X, Rm).

smulw({{bt,Y},{'cond',Cond},{r,Rd},{r,Rm},{r,Rs}}) ->
  smlaxy_form(Cond, 2#00010010, Rd, 0, Rs, Y, 1, Rm).

%%%
%%% Main Encode Dispatch
%%%

insn_encode(Op, Opnds) ->
  case Op of
    'adc' -> adc(Opnds);
    'add' -> add(Opnds);
    'and' -> 'and'(Opnds);
    'b' -> b(Opnds);
    'bic' -> bic(Opnds);
    'bkpt' -> bkpt(Opnds);
    'bl' -> bl(Opnds);
    'blx' -> blx(Opnds);
    'bx' -> bx(Opnds);
    'cdp' -> cdp(Opnds);
    'cdp2' -> cdp2(Opnds);
    'clz' -> clz(Opnds);
    'cmn' -> cmn(Opnds);
    'cmp' -> cmp(Opnds);
    'eor' -> eor(Opnds);
    'ldc' -> ldc(Opnds);
    'ldc2' -> ldc2(Opnds);
    'ldm' -> ldm(Opnds);
    'ldr' -> ldr(Opnds);
    'ldrb' -> ldrb(Opnds);
    'ldrd' -> ldrd(Opnds);
    %% ldrbt: omitted
    'ldrh' -> ldrh(Opnds);
    'ldrsb' -> ldrsb(Opnds);
    'ldrsh' -> ldrsh(Opnds);
    %% ldrt: omitted
    'mcr' -> mcr(Opnds);
    'mcr2' -> mcr2(Opnds);
    'mcrr' -> mcrr(Opnds);
    'mla' -> mla(Opnds);
    'mov' -> mov(Opnds);
    'mrc' -> mrc(Opnds);
    'mrc2' -> mrc2(Opnds);
    'mrrc' -> mrrc(Opnds);
    'mrs' -> mrs(Opnds);
    'msr' -> msr(Opnds);
    'mul' -> mul(Opnds);
    'mvn' -> mvn(Opnds);
    'orr' -> orr(Opnds);
    'pld' -> pld(Opnds);
    'qadd' -> qadd(Opnds);
    'qdadd' -> qdadd(Opnds);
    'qdsub' -> qdsub(Opnds);
    'qsub' -> qsub(Opnds);
    'rsb' -> rsb(Opnds);
    'rsc' -> rsc(Opnds);
    'sbc' -> sbc(Opnds);
    'smla' -> smla(Opnds);
    'smlal' -> smlal(Opnds); % may be regular ARM or DSP insn :-(
    'smlaw' -> smlaw(Opnds);
    'smull' -> smull(Opnds);
    'smul' -> smul(Opnds);
    'smulw' -> smulw(Opnds);
    'stc' -> stc(Opnds);
    'stc2' -> stc2(Opnds);
    'stm' -> stm(Opnds);
    'str' -> str(Opnds);
    'strb' -> strb(Opnds);
    %% strbt: omitted
    'strd' -> strd(Opnds);
    'strh' -> strh(Opnds);
    %% strt: omitted
    'sub' -> sub(Opnds);
    'swi' -> swi(Opnds);
    'swp' -> swp(Opnds);
    'swpb' -> swpb(Opnds);