ad9854par.lst

AD9854的C51控制程序

                     308     ; CHIRP mode
                     309     ; Clear FDATA in order not to enter hold mode 
                     310     ; Write to control register to enter chirp mode
                     311     ; FTW1 is still configured as 4MHz. Phase is the default 0 degree. 
                     312     ; delta FTW register and the ramp rate clock register are still 4KHz and 0x00C350.
                     313     ;======================================================================
                     314     
01F9                 315     CHIRP:          
01F9 C2A7            316                     CLR     FDATA
                     317     
                     318     ;write to control register to set chirp mode
                     319     
01FB 75A01D          320                     MOV     P2,#1DH         ; register address
A51 MACRO ASSEMBLER  AD9854PAR                                                            07/31/2007 11:02:24 PAGE     6

01FE 758010          321                     MOV     P0,#10H         ; 8 bits data
0201 C2B6            322                     CLR     WRITE           ; write enable
0203 D2B6            323                     SETB    WRITE   
                     324     
0205 75A01E          325                     MOV     P2,#1EH         ; register address
0208 758044          326                     MOV     P0,#44H         ; 8 bits data,master clock is multiplied by 4
020B C2B6            327                     CLR     WRITE           ; write enable
020D D2B6            328                     SETB    WRITE
                     329     
020F 75A01F          330                     MOV     P2,#1FH         ; register address
0212 758007          331                     MOV     P0,#07H         ; 8 bits data , chirp mode
0215 C2B6            332                     CLR     WRITE           ; write enable
0217 D2B6            333                     SETB    WRITE
                     334     
0219 75A020          335                     MOV     P2,#20H         ; register address
021C 758000          336                     MOV     P0,#00H         ; 8 bits data, SDO enabled
021F C2B6            337                     CLR     WRITE           ; write enable
0221 D2B6            338                     SETB    WRITE
                     339     
                     340     
0223 7464            341                     MOV     A,#64H          ; set delay period of 10s       
0225 5173            342                     CALL    DELAY           
0227 D2A7            343                     SETB    FDATA           ; enter hold mode
                     344                     
                     345     
0229 D3              346                     SETB    C
022A 40FE            347                     JC      $               ; INT0 leads to BPSK mode
                     348     
                     349     ;=====================================================================
                     350     ; BPSK mode
                     351     ; Write to control register to enter BPSK mode
                     352     ; FTW1 is still configured as 4MHz. 
                     353     ; Phase1 is the default 0 degree. Phase2 is configured as 90 degree.
                     354     ;======================================================================
                     355     
022C                 356     BPSK:
                     357     
                     358     ;write to control register to set BPSK mode
                     359     
022C 75A01D          360                     MOV     P2,#1DH         ; register address
022F 758010          361                     MOV     P0,#10H         ; 8 bits data
0232 C2B6            362                     CLR     WRITE           ; write enable
0234 D2B6            363                     SETB    WRITE
                     364     
0236 75A01E          365                     MOV     P2,#1EH         ; register address
0239 758044          366                     MOV     P0,#44H         ; 8 bits data,master clock is multiplied by 4
023C C2B6            367                     CLR     WRITE           ; write enable
023E D2B6            368                     SETB    WRITE
                     369     
0240 75A01F          370                     MOV     P2,#1FH         ; register address
0243 758009          371                     MOV     P0,#09H         ; 8 bits data, BPSK mode
0246 C2B6            372                     CLR     WRITE           ; write enable
0248 D2B6            373                     SETB    WRITE
                     374     
024A 75A020          375                     MOV     P2,#20H         ; register address
024D 758000          376                     MOV     P0,#00H         ; 8 bits data, SDO enabled
0250 C2B6            377                     CLR     WRITE           ; write enable
0252 D2B6            378                     SETB    WRITE
                     379     
                     380     ;write to phase2 register to 90 degree
                     381                     
0254 75A002          382                     MOV     P2,#02H         ; register address
0257 758010          383                     MOV     P0,#10H         ; 8 bits data
025A C2B6            384                     CLR     WRITE           ; write enable
025C D2B6            385                     SETB    WRITE
                     386     
A51 MACRO ASSEMBLER  AD9854PAR                                                            07/31/2007 11:02:24 PAGE     7

025E 75A003          387                     MOV     P2,#03H         ; register address
0261 758000          388                     MOV     P0,#00H         ; 8 bits data
0264 C2B6            389                     CLR     WRITE           ; write enable
0266 D2B6            390                     SETB    WRITE           
                     391             
                     392     
                     393     
0268 D3              394                     SETB    C               
0269 7414            395                     MOV     A,#14H          ;set delay period of 2s
                     396     
                     397     ;BY switching the BPSK pin status to implement the phase shift between 0 and 90 degree
                     398     
026B B2A7            399     GOBPSK:         CPL     FDATA
026D 5173            400                     CALL    DELAY
026F 40FA            401                     JC      GOBPSK          ; INT0 leads to another cycle
                     402     
0271 019A            403                     JMP SINGLETONE
                     404     
                     405     
                     406     ; Subroutines
                     407     
                     408     ;------------------------------------------------------------------
                     409     
                     410     
                     411     
0273                 412     DELAY:                                  ; Delays by 100ms * A
                     413                                             ; 100mSec based on 2.097152MHZ
                     414                                             ; Core Clock
                     415                                             ; i.e. default ADuC832 Clock
                     416     
0273 F9              417                     MOV     R1,A            ; Acc holds delay variable
0274 7A22            418      DLY0:          MOV     R2,#022h        ; Set up delay loop0
0276 7BFF            419      DLY1:          MOV     R3,#0FFh        ; Set up delay loop1
0278 DBFE            420                     DJNZ    R3,$            ; Dec R3 & Jump here until R3 is 0
027A DAFA            421                     DJNZ    R2,DLY1         ; Dec R2 & Jump DLY1 until R2 is 0
027C D9F6            422                     DJNZ    R1,DLY0         ; Dec R1 & Jump DLY0 until R1 is 0
027E 22              423                     RET                     ; Return from subroutine
                     424     
                     425     
                     426     
                     427     END
A51 MACRO ASSEMBLER  AD9854PAR                                                            07/31/2007 11:02:24 PAGE     8

SYMBOL TABLE LISTING
------ ----- -------


N A M E             T Y P E  V A L U E   ATTRIBUTES

BPSK . . . . . . .  C ADDR   022CH   A   
CHIRP. . . . . . .  C ADDR   01F9H   A   
DELAY. . . . . . .  C ADDR   0273H   A   
DLY0 . . . . . . .  C ADDR   0274H   A   
DLY1 . . . . . . .  C ADDR   0276H   A   
EA . . . . . . . .  B ADDR   00A8H.7 A   
EX0. . . . . . . .  B ADDR   00A8H.0 A   
FDATA. . . . . . .  B ADDR   00A0H.7 A   
FSK. . . . . . . .  C ADDR   0107H   A   
GOBPSK . . . . . .  C ADDR   026BH   A   
GOFSK. . . . . . .  C ADDR   016EH   A   
IT0. . . . . . . .  B ADDR   0088H.0 A   
MAIN . . . . . . .  C ADDR   0070H   A   
ORAMP. . . . . . .  B ADDR   00A0H.6 A   
P0 . . . . . . . .  D ADDR   0080H   A   
P2 . . . . . . . .  D ADDR   00A0H   A   
P3 . . . . . . . .  D ADDR   00B0H   A   
RAMPFSK. . . . . .  C ADDR   0174H   A   
READ . . . . . . .  B ADDR   00B0H.7 A   
RESET. . . . . . .  B ADDR   00B0H.4 A   
SINGLETONE . . . .  C ADDR   009AH   A   
SPSEL. . . . . . .  B ADDR   00B0H.5 A   
WRITE. . . . . . .  B ADDR   00B0H.6 A   


REGISTER BANK(S) USED: 0 


ASSEMBLY COMPLETE.  0 WARNING(S), 1 ERROR(S)