📄 ad9854par.lst
字号:
0100 D2AF 149 SETB EA ; enable inturrupts
0102 D2A8 150 SETB EX0 ; enable INT0
0104 D3 151 SETB C
0105 40FE 152 JC $ ; INT0 leads to unramped FSK mode
153
154 ;=====================================================================
155 ; unramped FSK mode
156 ; First program the control register to configure FSK mode
157 ; Then write to 48 bits FTW2 register to set output as 60MHz. FTW1 is still configured as
158 ; 4MHz.Phase is the default 0 degree.
159 ;======================================================================
160
0107 161 FSK:
162 ;write to control register to configure unramped FSK mode
0107 75A01D 163 MOV P2,#1DH ; register address
010A 758010 164 MOV P0,#10H ; 8 bits data
010D C2B6 165 CLR WRITE ; write enable
010F D2B6 166 SETB WRITE
167
0111 75A01E 168 MOV P2,#1EH ; register address
0114 758044 169 MOV P0,#44H ; 8 bits data, master clock is multiplied by 4
0117 C2B6 170 CLR WRITE ; write enable
0119 D2B6 171 SETB WRITE
172
011B 75A01F 173 MOV P2,#1FH ; register address
011E 758003 174 MOV P0,#03H ; 8 bits data, unramped FSK mode
0121 C2B6 175 CLR WRITE ; write enable
0123 D2B6 176 SETB WRITE
177
0125 75A020 178 MOV P2,#20H ; register address
0128 758000 179 MOV P0,#00H ; 8 bits data, SDO enabled
012B C2B6 180 CLR WRITE ; write enable
012D D2B6 181 SETB WRITE
182
183 ;write to FTW2 of 60MHz
012F 75A00A 184 MOV P2,#0AH ; register address
0132 75804C 185 MOV P0,#4CH ; 8 bits data
0135 C2B6 186 CLR WRITE ; write enable
0137 D2B6 187 SETB WRITE
188
A51 MACRO ASSEMBLER AD9854PAR 07/31/2007 11:02:24 PAGE 4
0139 75A00B 189 MOV P2,#0BH ; register address
013C 7580CC 190 MOV P0,#0CCH ; 8 bits data
013F C2B6 191 CLR WRITE ; write enable
0141 D2B6 192 SETB WRITE
193
0143 75A00C 194 MOV P2,#0CH ; register address
0146 7580CC 195 MOV P0,#0CCH ; 8 bits data
0149 C2B6 196 CLR WRITE ; write enable
014B D2B6 197 SETB WRITE
198
014D 75A00D 199 MOV P2,#0DH ; register address
0150 7580CC 200 MOV P0,#0CCH ; 8 bits data
0153 C2B6 201 CLR WRITE ; write enable
0155 D2B6 202 SETB WRITE
203
0157 75A00E 204 MOV P2,#0EH ; register address
015A 7580CC 205 MOV P0,#0CCH ; 8 bits data
015D C2B6 206 CLR WRITE ; write enable
015F D2B6 207 SETB WRITE
208
0161 75A00F 209 MOV P2,#0FH ; register address
0164 7580CC 210 MOV P0,#0CCH ; 8 bits data
0167 C2B6 211 CLR WRITE ; write enable
0169 D2B6 212 SETB WRITE
213
214
016B D3 215 SETB C
016C 7414 216 MOV A,#14H ; set delay period of 2s
217
218 ;BY switching the FSK pin status to implement the frequency shift between 4MHz and 60MHz
219
016E B2A7 220 GOFSK: CPL FDATA ; switch the FSK control pin status
0170 5173 221 CALL DELAY
0172 40FA 222 JC GOFSK ; INT0 will lead to ramped FSK mode
223
224 ;=====================================================================
225 ; ramped FSK mode
226 ; First program the control register to configure ramped FSK mode. Here we set the triangle
227 ; bit in the control register.
228 ; FTW1 and FTW2 are still configured as 4MHz and 60MHz. Phase is the default 0 degree.
229 ; Then program the delta FTW register and the ramp rate clock register as 4KHz and 0x00C350.
230 ;======================================================================
231
0174 232 RAMPFSK:
233 ; write to control register to configure ramped FSK mode
234
0174 75A01D 235 MOV P2,#1DH ; register address
0177 758010 236 MOV P0,#10H ; 8 bits data
017A C2B6 237 CLR WRITE ; write enable
017C D2B6 238 SETB WRITE
239
017E 75A01E 240 MOV P2,#1EH ; register address
0181 758044 241 MOV P0,#44H ; 8 bits data, master clock is multiplied by 4
0184 C2B6 242 CLR WRITE ; write enable
0186 D2B6 243 SETB WRITE
244
0188 75A01F 245 MOV P2,#1FH ; register address
018B 758025 246 MOV P0,#25H ; 8 bits data, ramped FSK mode, triangle bit is set
018E C2B6 247 CLR WRITE ; write enable
0190 D2B6 248 SETB WRITE
249
0192 75A020 250 MOV P2,#20H ; register address
0195 758000 251 MOV P0,#00H ; 8 bits data, SDO enabled
0198 C2B6 252 CLR WRITE ; write enable
019A D2B6 253 SETB WRITE
254
A51 MACRO ASSEMBLER AD9854PAR 07/31/2007 11:02:24 PAGE 5
255 ; write to delta FTW register
256
019C 75A010 257 MOV P2,#10H ; register address
019F 758000 258 MOV P0,#00H ; 8 bits data
01A2 C2B6 259 CLR WRITE ; write enable
01A4 D2B6 260 SETB WRITE
261
01A6 75A011 262 MOV P2,#11H ; register address
01A9 758001 263 MOV P0,#01H ; 8 bits data
01AC C2B6 264 CLR WRITE ; write enable
01AE D2B6 265 SETB WRITE
266
01B0 75A012 267 MOV P2,#12H ; register address
01B3 758004 268 MOV P0,#04H ; 8 bits data
01B6 C2B6 269 CLR WRITE ; write enable
01B8 D2B6 270 SETB WRITE
271
01BA 75A013 272 MOV P2,#13H ; register address
01BD 75808B 273 MOV P0,#08BH ; 8 bits data
01C0 C2B6 274 CLR WRITE ; write enable
01C2 D2B6 275 SETB WRITE
276
01C4 75A014 277 MOV P2,#14H ; register address
01C7 758058 278 MOV P0,#058H ; 8 bits data
01CA C2B6 279 CLR WRITE ; write enable
01CC D2B6 280 SETB WRITE
281
01CE 75A015 282 MOV P2,#15H ; register address
01D1 75808E 283 MOV P0,#08EH ; 8 bits data
01D4 C2B6 284 CLR WRITE ; write enable
01D6 D2B6 285 SETB WRITE
286
287 ; write to ramp rate clock register
288
01D8 75A01A 289 MOV P2,#1AH ; register address
01DB 758000 290 MOV P0,#00H ; 8 bits data
01DE C2B6 291 CLR WRITE ; write enable
01E0 D2B6 292 SETB WRITE
293
01E2 75A01B 294 MOV P2,#1BH ; register address
01E5 7580C3 295 MOV P0,#0C3H ; 8 bits data
01E8 C2B6 296 CLR WRITE ; write enable
01EA D2B6 297 SETB WRITE
298
01EC 75A01C 299 MOV P2,#1CH ; register address
01EF 758050 300 MOV P0,#50H ; 8 bits data
01F2 C2B6 301 CLR WRITE ; write enable
01F4 D2B6 302 SETB WRITE
303
01F6 D3 304 SETB C
01F7 40FE 305 JC $ ; INT0 leads to CHIRP mode
306
307 ;=====================================================================
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