📄 ad9854par.lst
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A51 MACRO ASSEMBLER AD9854PAR 07/31/2007 11:02:24 PAGE 1
MACRO ASSEMBLER A51 V8.00
OBJECT MODULE PLACED IN .\ad9854Par.obj
ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE C:\Documents and Settings\Administrator\桌面\ad9854Par.asm SET(SMALL) DEBU
G PRINT(.\ad9854Par.lst) OBJECT(.\ad9854Par.obj) EP
LOC OBJ LINE SOURCE
1 ;======================================================================
2 ;
3 ; Author : ADI CAST, china.support@analog.com
4 ;
5 ; Date : June 2003
6 ;
7 ; File : ad9854P.asm
8 ;
9 ; Description : parallel control mode. Internal update clock .
10 ; The program can implement the basic four modes of ad9854:
11 ; single tone, unramped FSK, ramped FSK, chirp, BPSK.
12 ; we assume that master clock is 50 MHz and multiplied by 4
13 ; ADUC832 is used to control ad9854. The core clock is 2.097152MHz.
14 ;======================================================================
15
16 $mod832 ; Use ADuC832 predefined Symbols
*** ERROR #A68 IN 16 (C:\Documents and Settings\Administrator\桌面\ad9854Par.asm, LINE 16): UNKNOWN CONTROL OR BAD ARGUMENT(S)
17
18 ;======================================================================
19 ;DEFINE CONTROL PINS OF ADUC832 FOR THE PURPOSE OF AD9854 CONTROL.
20 ;Customers should define the pins according to their design.
21 ;If P0 is used as the control port, pull-up resistors should be added to each pin of P0.
22 ;======================================================================
23
24 ;======================================================================
25 ;P0 is used as the eight bits data port.
26 ;p2.0~p2.5 is used to give the register address
27 ;======================================================================
28
00B4 29 RESET EQU P3.4 ; master reset of AD9854
00B5 30 SPSEL EQU P3.5 ; serial/parrelel select pin
00A7 31 FDATA EQU P2.7 ; multi-function pin for different modes
00A6 32 ORAMP EQU P2.6 ; output shape pin
00B6 33 WRITE EQU P3.6 ; write signal
00B7 34 READ EQU P3.7 ; read signal
35
36 ;======================================================================
37
---- 38 CSEG ; Defines the following as a segment of code
39
0000 40 ORG 0000H ; Load Code at address'0'
41
0000 806E 42 JMP MAIN ; Jump to MAIN
43
44 ;======================================================================
45
0003 46 ORG 0003h ; (INT0 ISR)
47
0003 C3 48 CLR C
0004 32 49 RETI ; Return from Interrupt
50
51 ;======================================================================
52
0070 53 ORG 0070h
54
0070 55 MAIN: ; (main program)
56
A51 MACRO ASSEMBLER AD9854PAR 07/31/2007 11:02:24 PAGE 2
57 ;======================================================================
58 ;initialization
59 ;after reset of aduc832, the default status of IO ports are 0xFFH
60 ;======================================================================
0070 C2B4 61 CLR RESET ;disable reset
62
63
64 ;======================================================================
65 ; write to update clock register as 40KHz.
66 ; It can be changed by customers according to their requirement
67 ;======================================================================
68
0072 75A016 69 MOV P2,#16H ; the register address
0075 758000 70 MOV P0,#00H ; the higher 8 bits, MSB firsts
0078 C2B6 71 CLR WRITE ; write enabled
007A D2B6 72 SETB WRITE
73
007C 75A017 74 MOV P2,#17H ; the register address
007F 758000 75 MOV P0,#00H ; 8 bits data
0082 C2B6 76 CLR WRITE ; write enabled
0084 D2B6 77 SETB WRITE
78
0086 75A018 79 MOV P2,#18H ; the register address
0089 758009 80 MOV P0,#09H ; 8 bits data
008C C2B6 81 CLR WRITE ; write enabled
008E D2B6 82 SETB WRITE
83
0090 75A019 84 MOV P2,#19H ; the register address
0093 7580C3 85 MOV P0,#0c3H ; 8 bits data
0096 C2B6 86 CLR WRITE ; write enabled
0098 D2B6 87 SETB WRITE
88
89 ;=====================================================================
90 ; Single tone mode
91 ; First program the control register to configure single tone mode
92 ; Then write to 48 bits FTW1 register to set output as 4MHz. Phase is the default 0 degree.
93 ;======================================================================
009A 94 SINGLETONE:
95 ;write to control register to set single tone mode
009A 75A01D 96 MOV P2,#1DH ; register address
009D 758010 97 MOV P0,#10H ; 8 bits data
00A0 C2B6 98 CLR WRITE ; write enable
00A2 D2B6 99 SETB WRITE
100
00A4 75A01E 101 MOV P2,#1EH ; register address
00A7 758044 102 MOV P0,#44H ; 8 bits data, master clock multiplied by 4
00AA C2B6 103 CLR WRITE ; write enable
00AC D2B6 104 SETB WRITE
105
00AE 75A01F 106 MOV P2,#1FH ; register address
00B1 758001 107 MOV P0,#01H ; 8 bits data, single tone mode
00B4 C2B6 108 CLR WRITE ; write enable
00B6 D2B6 109 SETB WRITE
110
00B8 75A020 111 MOV P2,#20H ; register address
00BB 758000 112 MOV P0,#00H ; 8 bits data, SDO enabled
00BE C2B6 113 CLR WRITE ; write enable
00C0 D2B6 114 SETB WRITE
115
116 ;write to FTW1 register as 4MHz
117
00C2 75A004 118 MOV P2,#04H ; register address
00C5 758005 119 MOV P0,#05H ; 8 bits data
00C8 C2B6 120 CLR WRITE ; write enable
00CA D2B6 121 SETB WRITE
122
A51 MACRO ASSEMBLER AD9854PAR 07/31/2007 11:02:24 PAGE 3
00CC 75A005 123 MOV P2,#05H ; register address
00CF 75801E 124 MOV P0,#1EH ; 8 bits data
00D2 C2B6 125 CLR WRITE ; write enable
00D4 D2B6 126 SETB WRITE
127
00D6 75A006 128 MOV P2,#06H ; register address
00D9 7580B8 129 MOV P0,#0B8H ; 8 bits data
00DC C2B6 130 CLR WRITE ; write enable
00DE D2B6 131 SETB WRITE
132
00E0 75A007 133 MOV P2,#07H ; register address
00E3 758051 134 MOV P0,#51H ; 8 bits data
00E6 C2B6 135 CLR WRITE ; write enable
00E8 D2B6 136 SETB WRITE
137
00EA 75A008 138 MOV P2,#08H ; register address
00ED 7580EB 139 MOV P0,#0EBH ; 8 bits data
00F0 C2B6 140 CLR WRITE ; write enable
00F2 D2B6 141 SETB WRITE
142
00F4 75A009 143 MOV P2,#09H ; register address
00F7 758085 144 MOV P0,#85H ; 8 bits data
00FA C2B6 145 CLR WRITE ; write enable
00FC D2B6 146 SETB WRITE
147
00FE D288 148 SETB IT0 ; INT0 edge triggered
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