📄 s3c44b0x.s
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;// <o5.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o5.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o5.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o5.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o5.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o5.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o5.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;//
;// <h> Bank 6
;// <o10.0..2> BK76MAP: Bank 6/7 Memory Map
;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M
;// <o8.24..25> DW: Data Bus Width
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
;// <o8.26> WS: WAIT Status
;// <0=> WAIT Disable
;// <1=> WAIT Enable
;// <o8.27> ST: SRAM Type
;// <0=> Not using UB/LB
;// <1=> Using UB/LB
;// <o6.15..16> MT: Memory Type
;// <0=> ROM or SRAM
;// <1=> FP DRAMP
;// <2=> EDO DRAM
;// <3=> SDRAM
;// <h> ROM or SRAM
;// <o6.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o6.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o6.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o6.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o6.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o6.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o6.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;// <h> FP DRAM or EDO DRAM
;// <o6.0..1> CAN: Columnn Address Number
;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit
;// <o6.2> Tcp: CAS Pre-charge
;// <0=> 1 clk <1=> 2 clks
;// <o6.3> Tcas: CAS Pulse Width
;// <0=> 1 clk <1=> 2 clks
;// <o6.4..5> Trcd: RAS to CAS Delay
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// </h>
;// <h> SDRAM
;// <o6.0..1> SCAN: Columnn Address Number
;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd
;// <o6.2..3> Trcd: RAS to CAS Delay
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd
;// <o10.4> SCLKEN: SCLK Selection (Bank 6/7)
;// <0=> Normal
;// <1=> Reduced Power
;// <o11.0..2> BL: Burst Length
;// <0=> 1
;// <o11.3> BT: Burst Type
;// <0=> Sequential
;// <o11.4..6> CL: CAS Latency
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks
;// <o11.7..8> TM: Test Mode
;// <0=> Mode Register Set
;// <o11.9> WBL: Write Burst Length
;// <0=> 0
;// </h>
;// </h>
;//
;// <h> Bank 7
;// <o10.0..2> BK76MAP: Bank 6/7 Memory Map
;// <0=> 32M <4=> 2M <5=> 4M <6=> 8M <7=> 16M
;// <o8.28..29> DW: Data Bus Width
;// <0=> 8-bit <1=> 16-bit <2=> 32-bit <3=> Rsrvd
;// <o8.30> WS: WAIT Status
;// <0=> WAIT Disable
;// <1=> WAIT Enable
;// <o8.31> ST: SRAM Type
;// <0=> Not using UB/LB
;// <1=> Using UB/LB
;// <o7.15..16> MT: Memory Type
;// <0=> ROM or SRAM
;// <1=> FP DRAMP
;// <2=> EDO DRAM
;// <3=> SDRAM
;// <h> ROM or SRAM
;// <o7.0..1> PMC: Page Mode Configuration
;// <0=> 1 Data <1=> 4 Data <2=> 8 Data <3=> 16 Data
;// <o7.2..3> Tpac: Page Mode Access Cycle
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> 6 clks
;// <o7.4..5> Tcah: Address Holding Time after nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o7.6..7> Toch: Chip Select Hold on nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o7.8..10> Tacc: Access Cycle
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <4=> 6 clk <5=> 8 clks <6=> 10 clks <7=> 14 clks
;// <o7.11..12> Tcos: Chip Select Set-up nOE
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// <o7.13..14> Tacs: Address Set-up before nGCSn
;// <0=> 0 clk <1=> 1 clk <2=> 2 clks <3=> 4 clks
;// </h>
;// <h> FP DRAM or EDO DRAM
;// <o7.0..1> CAN: Columnn Address Number
;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> 11-bit
;// <o7.2> Tcp: CAS Pre-charge
;// <0=> 1 clk <1=> 2 clks
;// <o7.3> Tcas: CAS Pulse Width
;// <0=> 1 clk <1=> 2 clks
;// <o7.4..5> Trcd: RAS to CAS Delay
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// </h>
;// <h> SDRAM
;// <o7.0..1> SCAN: Columnn Address Number
;// <0=> 8-bit <1=> 9-bit <2=> 10-bit <3=> Rsrvd
;// <o7.2..3> Trcd: RAS to CAS Delay
;// <0=> 2 clks <1=> 3 clks <2=> 4 clks <3=> Rsrvd
;// <o10.4> SCLKEN: SCLK Selection (Bank 6/7)
;// <0=> Normal
;// <1=> Reduced Power
;// <o12.0..2> BL: Burst Length
;// <0=> 1
;// <o12.3> BT: Burst Type
;// <0=> Sequential
;// <o12.4..6> CL: CAS Latency
;// <0=> 1 clk <1=> 2 clks <2=> 3 clks
;// <o12.7..8> TM: Test Mode
;// <0=> Mode Register Set
;// <o12.9> WBL: Write Burst Length
;// <0=> 0
;// </h>
;// </h>
;//
;// <h> Refresh
;// <o9.23> REFEN: DRAM/SDRAM Refresh
;// <0=> Disable <1=> Enable
;// <o9.22> TREFMD: DRAM/SDRAM Refresh Mode
;// <0=> CBR/Auto Refresh
;// <1=> Self Refresh
;// <o9.20..21> Trp: DRAM/SDRAM RAS Pre-charge Time
;// <0=> 1.5 clks (DRAM) / 2 clks (SDRAM)
;// <1=> 2.5 clks (DRAM) / 3 clks (SDRAM)
;// <2=> 3.5 clks (DRAM) / 4 clks (SDRAM)
;// <3=> 4.5 clks (DRAM) / Rsrvd (SDRAM)
;// <o9.18..19> Trc: SDRAM RC Min Time
;// <0=> 4 clks <1=> 5 clks <2=> 6 clks <3=> 7 clks
;// <o9.16..17> Tchr: DRAM CAS Hold Time
;// <0=> 1 clks <1=> 2 clks <2=> 3 clks <3=> 4 clks
;// <o9.0..10> Refresh Counter <0x0-0x07FF>
;// <i> Refresh Period = (2^11 - Refresh Count + 1) / MCLK
;// </h>
BANKCON0_Val EQU 0x00001900
BANKCON1_Val EQU 0x00000700
BANKCON2_Val EQU 0x00000700
BANKCON3_Val EQU 0x00000700
BANKCON4_Val EQU 0x00000700
BANKCON5_Val EQU 0x00000700
BANKCON6_Val EQU 0x00018000
BANKCON7_Val EQU 0x00018008
BWSCON_Val EQU 0x11111110
REFRESH_Val EQU 0x00AC0459
BANKSIZE_Val EQU 0x00000004
MRSRB6_Val EQU 0x00000020
MRSRB7_Val EQU 0x00000000
;// </e> End of MC
; I/O Ports definitions
PIO_BASE EQU 0x01D20000 ; PIO Base Address
PCONA_OFS EQU 0x00 ; PCONA Offset
PCONB_OFS EQU 0x08 ; PCONB Offset
PCONC_OFS EQU 0x10 ; PCONC Offset
PCOND_OFS EQU 0x1C ; PCOND Offset
PCONE_OFS EQU 0x28 ; PCONE Offset
PCONF_OFS EQU 0x34 ; PCONF Offset
PCONG_OFS EQU 0x40 ; PCONG Offset
PUPC_OFS EQU 0x18 ; PUPC Offset
PUPD_OFS EQU 0x24 ; PUPD Offset
PUPE_OFS EQU 0x30 ; PUPE Offset
PUPF_OFS EQU 0x3C ; PUPF Offset
PUPG_OFS EQU 0x48 ; PUPG Offset
SPUCR_OFS EQU 0x4C ; SPUCR Offset
;// <e> I/O Configuration
PIO_SETUP EQU 1
;// <e> Port A
;// <o1.0> PA0 <0=> Output <1=> ADDR0
;// <o1.1> PA1 <0=> Output <1=> ADDR16
;// <o1.2> PA2 <0=> Output <1=> ADDR17
;// <o1.3> PA3 <0=> Output <1=> ADDR18
;// <o1.4> PA4 <0=> Output <1=> ADDR19
;// <o1.5> PA5 <0=> Output <1=> ADDR20
;// <o1.6> PA6 <0=> Output <1=> ADDR21
;// <o1.7> PA7 <0=> Output <1=> ADDR22
;// <o1.8> PA8 <0=> Output <1=> ADDR23
;// <o1.9> PA9 <0=> Output <1=> ADDR24
;// </e>
PIOA_SETUP EQU 1
PCONA_Val EQU 0x000003FF
;// <e> Port B
;// <o1.0> PB0 <0=> Output <1=> SCKE
;// <o1.1> PB1 <0=> Output <1=> CKLK
;// <o1.2> PB2 <0=> Output <1=> nSCAS/nCAS2
;// <o1.3> PB3 <0=> Output <1=> nSRAS/nCAS3
;// <o1.4> PB4 <0=> Output <1=> nWBE2/nBE2/DQM2
;// <o1.5> PB5 <0=> Output <1=> nWBE3/nBE3/DQM3
;// <o1.6> PB6 <0=> Output <1=> nGCS1
;// <o1.7> PB7 <0=> Output <1=> nGCS2
;// <o1.8> PB8 <0=> Output <1=> nGCS3
;// <o1.9> PB9 <0=> Output <1=> nGCS4
;// <o1.10> PB10 <0=> Output <1=> nGCS5
;// </e>
PIOB_SETUP EQU 1
PCONB_Val EQU 0x000007FF
;// <e> Port C
;// <o1.0..1> PC0 <0=> Input <1=> Output <2=> DATA16 <3=> IISLRCK
;// <o1.2..3> PC1 <0=> Input <1=> Output <2=> DATA17 <3=> IISDO
;// <o1.4..5> PC2 <0=> Input <1=> Output <2=> DATA18 <3=> IISDI
;// <o1.6..7> PC3 <0=> Input <1=> Output <2=> DATA19 <3=> IISCLK
;// <o1.8..9> PC4 <0=> Input <1=> Output <2=> DATA20 <3=> VD7
;// <o1.10..11> PC5 <0=> Input <1=> Output <2=> DATA21 <3=> VD6
;// <o1.12..13> PC6 <0=> Input <1=> Output <2=> DATA22 <3=> VD5
;// <o1.14..15> PC7 <0=> Input <1=> Output <2=> DATA23 <3=> VD4
;// <o1.16..17> PC8 <0=> Input <1=> Output <2=> DATA24 <3=> nXDACK1
;// <o1.18..19> PC9 <0=> Input <1=> Output <2=> DATA25 <3=> nXDREQ1
;// <o1.20..21> PC10 <0=> Input <1=> Output <2=> DATA26 <3=> nRTS1
;// <o1.22..23> PC11 <0=> Input <1=> Output <2=> DATA27 <3=> nCTS1
;// <o1.24..25> PC12 <0=> Input <1=> Output <2=> DATA28 <3=> TxD1
;// <o1.26..27> PC13 <0=> Input <1=> Output <2=> DATA29 <3=> RxD1
;// <o1.28..29> PC14 <0=> Input <1=> Output <2=> DATA30 <3=> nRTS0
;// <o1.30..31> PC15 <0=> Input <1=> Output <2=> DATA31 <3=> nCTS0
;// <h> Pull-up Resistors
;// <o2.0> PC0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PC1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PC2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PC3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PC4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PC5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PC6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PC7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PC8 Pull-up <0=> Enabled <1=> Disabled
;// <o2.9> PC9 Pull-up <0=> Enabled <1=> Disabled
;// <o2.10> PC10 Pull-up <0=> Enabled <1=> Disabled
;// <o2.11> PC11 Pull-up <0=> Enabled <1=> Disabled
;// <o2.12> PC12 Pull-up <0=> Enabled <1=> Disabled
;// <o2.13> PC13 Pull-up <0=> Enabled <1=> Disabled
;// <o2.14> PC14 Pull-up <0=> Enabled <1=> Disabled
;// <o2.15> PC15 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOC_SETUP EQU 1
PCONC_Val EQU 0xF0000000
PUPC_Val EQU 0x00000000
;// <e> Port D
;// <o1.0..1> PD0 <0=> Input <1=> Output <2=> VD0 <3=> Reserved
;// <o1.2..3> PD1 <0=> Input <1=> Output <2=> VD1 <3=> Reserved
;// <o1.4..5> PD2 <0=> Input <1=> Output <2=> VD2 <3=> Reserved
;// <o1.6..7> PD3 <0=> Input <1=> Output <2=> VD3 <3=> Reserved
;// <o1.8..9> PD4 <0=> Input <1=> Output <2=> VCLK <3=> Reserved
;// <o1.10..11> PD5 <0=> Input <1=> Output <2=> VLINE <3=> Reserved
;// <o1.12..13> PD6 <0=> Input <1=> Output <2=> VM <3=> Reserved
;// <o1.14..15> PD7 <0=> Input <1=> Output <2=> VFRAME <3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PD0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PD1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PD2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PD3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PD4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PD5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PD6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PD7 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOD_SETUP EQU 1
PCOND_Val EQU 0x00000000
PUPD_Val EQU 0x00000000
;// <e> Port E
;// <o1.0..1> PE0 <0=> Input <1=> Output <2=> Fpllo <3=> Fout
;// <o1.2..3> PE1 <0=> Input <1=> Output <2=> TxD0 <3=> Reserved
;// <o1.4..5> PE2 <0=> Input <1=> Output <2=> RxD0 <3=> Reserved
;// <o1.6..7> PE3 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved
;// <o1.8..9> PE4 <0=> Input <1=> Output <2=> TOUT1 <3=> TCLK
;// <o1.10..11> PE5 <0=> Input <1=> Output <2=> TOUT2 <3=> TCLK
;// <o1.12..13> PE6 <0=> Input <1=> Output <2=> TOUT3 <3=> VD6
;// <o1.14..15> PE7 <0=> Input <1=> Output <2=> TOUT4 <3=> VD7
;// <o1.16..17> PE8 <0=> Input <1=> Output <2=> CODECLK <3=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PE0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PE1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PE2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PE3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PE4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PE5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PE6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PE7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PE8 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOE_SETUP EQU 1
PCONE_Val EQU 0x00000029
PUPE_Val EQU 0x00000000
;// <e> Port F
;// <o1.0..1> PF0 <0=> Input <1=> Output <2=> IICSCL <3=> Reserved
;// <o1.2..3> PF1 <0=> Input <1=> Output <2=> IICSDA <3=> Reserved
;// <o1.4..5> PF2 <0=> Input <1=> Output <2=> nWAIT <3=> Reserved
;// <o1.6..7> PF3 <0=> Input <1=> Output <2=> nXBACK <3=> nXDACK0
;// <o1.8..9> PF4 <0=> Input <1=> Output <2=> nXBREQ <3=> nXDREQ0
;// <o1.10..12> PF5 <0=> Input <1=> Output <2=> nRTS1 <3=> SIOTxD
;// <4=> IISLRCK <5=> Reserved <6=> Reserved <7=> Reserved
;// <o1.13..15> PF6 <0=> Input <1=> Output <2=> TxD1 <3=> SIORDY
;// <4=> IISDO <5=> Reserved <6=> Reserved <7=> Reserved
;// <o1.16..18> PF7 <0=> Input <1=> Output <2=> RxD1 <3=> SIORxD
;// <4=> IISDI <5=> Reserved <6=> Reserved <7=> Reserved
;// <o1.19..21> PF8 <0=> Input <1=> Output <2=> nCTS1 <3=> SIOCLK
;// <4=> IISCLK <5=> Reserved <6=> Reserved <7=> Reserved
;// <h> Pull-up Resistors
;// <o2.0> PF0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PF1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PF2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PF3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PF4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PF5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PF6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PF7 Pull-up <0=> Enabled <1=> Disabled
;// <o2.8> PF8 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOF_SETUP EQU 1
PCONF_Val EQU 0x00000000
PUPF_Val EQU 0x00000000
;// <e> Port G
;// <o1.0..1> PG0 <0=> Input <1=> Output <2=> VD4 <3=> EINT0
;// <o1.2..3> PG1 <0=> Input <1=> Output <2=> VD5 <3=> EINT1
;// <o1.4..5> PG2 <0=> Input <1=> Output <2=> nCTS0 <3=> EINT2
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