spi3310.tan.qmsg

FPGA模拟SPI接口驱动3310液晶屏的 详细驱动

{ "Info" "ITDB_FULL_TCO_RESULT" "clk ce main:inst\|ce_out 13.938 ns register " "Info: tco from clock \"clk\" to destination pin \"ce\" through register \"main:inst\|ce_out\" is 13.938 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.792 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns clk 1 CLK PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 80 24 192 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.293 ns clk~clkctrl 2 COMB CLKCTRL_G6 33 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.293 ns; Loc. = CLKCTRL_G6; Fanout = 33; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 80 24 192 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.832 ns) + CELL(0.970 ns) 3.095 ns clk:inst6\|f500k 3 REG LCFF_X12_Y8_N29 3 " "Info: 3: + IC(0.832 ns) + CELL(0.970 ns) = 3.095 ns; Loc. = LCFF_X12_Y8_N29; Fanout = 3; REG Node = 'clk:inst6\|f500k'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.802 ns" { clk~clkctrl clk:inst6|f500k } "NODE_NAME" } } { "clk.v" "" { Text "E:/FPGA/work/spi3310/clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.178 ns) + CELL(0.000 ns) 5.273 ns clk:inst6\|f500k~clkctrl 4 COMB CLKCTRL_G5 59 " "Info: 4: + IC(2.178 ns) + CELL(0.000 ns) = 5.273 ns; Loc. = CLKCTRL_G5; Fanout = 59; COMB Node = 'clk:inst6\|f500k~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.178 ns" { clk:inst6|f500k clk:inst6|f500k~clkctrl } "NODE_NAME" } } { "clk.v" "" { Text "E:/FPGA/work/spi3310/clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.853 ns) + CELL(0.666 ns) 6.792 ns main:inst\|ce_out 5 REG LCFF_X17_Y11_N23 2 " "Info: 5: + IC(0.853 ns) + CELL(0.666 ns) = 6.792 ns; Loc. = LCFF_X17_Y11_N23; Fanout = 2; REG Node = 'main:inst\|ce_out'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.519 ns" { clk:inst6|f500k~clkctrl main:inst|ce_out } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.786 ns ( 41.02 % ) " "Info: Total cell delay = 2.786 ns ( 41.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.006 ns ( 58.98 % ) " "Info: Total interconnect delay = 4.006 ns ( 58.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.792 ns" { clk clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|ce_out } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.792 ns" { clk clk~combout clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|ce_out } { 0.000ns 0.000ns 0.143ns 0.832ns 2.178ns 0.853ns } { 0.000ns 1.150ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 3 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.842 ns + Longest register pin " "Info: + Longest register to pin delay is 6.842 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns main:inst\|ce_out 1 REG LCFF_X17_Y11_N23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y11_N23; Fanout = 2; REG Node = 'main:inst\|ce_out'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { main:inst|ce_out } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.462 ns) + CELL(0.206 ns) 1.668 ns inst4 2 COMB LCCOMB_X19_Y12_N24 1 " "Info: 2: + IC(1.462 ns) + CELL(0.206 ns) = 1.668 ns; Loc. = LCCOMB_X19_Y12_N24; Fanout = 1; COMB Node = 'inst4'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.668 ns" { main:inst|ce_out inst4 } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 328 704 768 376 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.078 ns) + CELL(3.096 ns) 6.842 ns ce 3 PIN PIN_137 0 " "Info: 3: + IC(2.078 ns) + CELL(3.096 ns) = 6.842 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'ce'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.174 ns" { inst4 ce } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 344 808 984 360 "ce" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.302 ns ( 48.26 % ) " "Info: Total cell delay = 3.302 ns ( 48.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.540 ns ( 51.74 % ) " "Info: Total interconnect delay = 3.540 ns ( 51.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.842 ns" { main:inst|ce_out inst4 ce } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.842 ns" { main:inst|ce_out inst4 ce } { 0.000ns 1.462ns 2.078ns } { 0.000ns 0.206ns 3.096ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.792 ns" { clk clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|ce_out } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.792 ns" { clk clk~combout clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|ce_out } { 0.000ns 0.000ns 0.143ns 0.832ns 2.178ns 0.853ns } { 0.000ns 1.150ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.842 ns" { main:inst|ce_out inst4 ce } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.842 ns" { main:inst|ce_out inst4 ce } { 0.000ns 1.462ns 2.078ns } { 0.000ns 0.206ns 3.096ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 22 18:19:04 2007 " "Info: Processing ended: Sat Dec 22 18:19:04 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}