📄 spi3310.tan.qmsg

📁 FPGA模拟SPI接口驱动3310液晶屏的详细驱动
💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 80 24 192 96 "clk" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk:inst6\|f500k " "Info: Detected ripple clock \"clk:inst6\|f500k\" as buffer" {  } { { "clk.v" "" { Text "E:/FPGA/work/spi3310/clk.v" 3 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk:inst6\|f500k" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register main:inst\|i\[6\] register main:inst\|data_out\[7\] 106.26 MHz 9.411 ns Internal " "Info: Clock \"clk\" has Internal fmax of 106.26 MHz between source register \"main:inst\|i\[6\]\" and destination register \"main:inst\|data_out\[7\]\" (period= 9.411 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.145 ns + Longest register register " "Info: + Longest register to register delay is 9.145 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns main:inst\|i\[6\] 1 REG LCFF_X19_Y11_N23 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y11_N23; Fanout = 19; REG Node = 'main:inst\|i\[6\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { main:inst|i[6] } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.789 ns) + CELL(0.647 ns) 1.436 ns main:inst\|LessThan13~157 2 COMB LCCOMB_X19_Y11_N4 3 " "Info: 2: + IC(0.789 ns) + CELL(0.647 ns) = 1.436 ns; Loc. = LCCOMB_X19_Y11_N4; Fanout = 3; COMB Node = 'main:inst\|LessThan13~157'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.436 ns" { main:inst|i[6] main:inst|LessThan13~157 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.103 ns) + CELL(0.615 ns) 3.154 ns main:inst\|LessThan13~159 3 COMB LCCOMB_X18_Y12_N12 2 " "Info: 3: + IC(1.103 ns) + CELL(0.615 ns) = 3.154 ns; Loc. = LCCOMB_X18_Y12_N12; Fanout = 2; COMB Node = 'main:inst\|LessThan13~159'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.718 ns" { main:inst|LessThan13~157 main:inst|LessThan13~159 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.614 ns) 4.175 ns main:inst\|Selector7~214 4 COMB LCCOMB_X18_Y12_N18 4 " "Info: 4: + IC(0.407 ns) + CELL(0.614 ns) = 4.175 ns; Loc. = LCCOMB_X18_Y12_N18; Fanout = 4; COMB Node = 'main:inst\|Selector7~214'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.021 ns" { main:inst|LessThan13~159 main:inst|Selector7~214 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.544 ns) 5.100 ns main:inst\|Selector28~40 5 COMB LCCOMB_X18_Y12_N20 2 " "Info: 5: + IC(0.381 ns) + CELL(0.544 ns) = 5.100 ns; Loc. = LCCOMB_X18_Y12_N20; Fanout = 2; COMB Node = 'main:inst\|Selector28~40'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.925 ns" { main:inst|Selector7~214 main:inst|Selector28~40 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.370 ns) 5.861 ns main:inst\|Selector32~46 6 COMB LCCOMB_X18_Y12_N0 2 " "Info: 6: + IC(0.391 ns) + CELL(0.370 ns) = 5.861 ns; Loc. = LCCOMB_X18_Y12_N0; Fanout = 2; COMB Node = 'main:inst\|Selector32~46'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.761 ns" { main:inst|Selector28~40 main:inst|Selector32~46 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.384 ns) + CELL(0.206 ns) 6.451 ns main:inst\|Selector26~18 7 COMB LCCOMB_X18_Y12_N30 2 " "Info: 7: + IC(0.384 ns) + CELL(0.206 ns) = 6.451 ns; Loc. = LCCOMB_X18_Y12_N30; Fanout = 2; COMB Node = 'main:inst\|Selector26~18'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.590 ns" { main:inst|Selector32~46 main:inst|Selector26~18 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.206 ns) 7.030 ns main:inst\|WideNor0~61 8 COMB LCCOMB_X18_Y12_N24 4 " "Info: 8: + IC(0.373 ns) + CELL(0.206 ns) = 7.030 ns; Loc. = LCCOMB_X18_Y12_N24; Fanout = 4; COMB Node = 'main:inst\|WideNor0~61'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.579 ns" { main:inst|Selector26~18 main:inst|WideNor0~61 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.319 ns) 7.746 ns main:inst\|WideOr22 9 COMB LCCOMB_X18_Y12_N8 9 " "Info: 9: + IC(0.397 ns) + CELL(0.319 ns) = 7.746 ns; Loc. = LCCOMB_X18_Y12_N8; Fanout = 9; COMB Node = 'main:inst\|WideOr22'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.716 ns" { main:inst|WideNor0~61 main:inst|WideOr22 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.085 ns) + CELL(0.206 ns) 9.037 ns main:inst\|Selector21~10 10 COMB LCCOMB_X18_Y11_N22 1 " "Info: 10: + IC(1.085 ns) + CELL(0.206 ns) = 9.037 ns; Loc. = LCCOMB_X18_Y11_N22; Fanout = 1; COMB Node = 'main:inst\|Selector21~10'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.291 ns" { main:inst|WideOr22 main:inst|Selector21~10 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.145 ns main:inst\|data_out\[7\] 11 REG LCFF_X18_Y11_N23 2 " "Info: 11: + IC(0.000 ns) + CELL(0.108 ns) = 9.145 ns; Loc. = LCFF_X18_Y11_N23; Fanout = 2; REG Node = 'main:inst\|data_out\[7\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { main:inst|Selector21~10 main:inst|data_out[7] } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 278 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.835 ns ( 41.94 % ) " "Info: Total cell delay = 3.835 ns ( 41.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.310 ns ( 58.06 % ) " "Info: Total interconnect delay = 5.310 ns ( 58.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.145 ns" { main:inst|i[6] main:inst|LessThan13~157 main:inst|LessThan13~159 main:inst|Selector7~214 main:inst|Selector28~40 main:inst|Selector32~46 main:inst|Selector26~18 main:inst|WideNor0~61 main:inst|WideOr22 main:inst|Selector21~10 main:inst|data_out[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "9.145 ns" { main:inst|i[6] main:inst|LessThan13~157 main:inst|LessThan13~159 main:inst|Selector7~214 main:inst|Selector28~40 main:inst|Selector32~46 main:inst|Selector26~18 main:inst|WideNor0~61 main:inst|WideOr22 main:inst|Selector21~10 main:inst|data_out[7] } { 0.000ns 0.789ns 1.103ns 0.407ns 0.381ns 0.391ns 0.384ns 0.373ns 0.397ns 1.085ns 0.000ns } { 0.000ns 0.647ns 0.615ns 0.614ns 0.544ns 0.370ns 0.206ns 0.206ns 0.319ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.002 ns - Smallest " "Info: - Smallest clock skew is -0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.793 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns clk 1 CLK PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 80 24 192 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.293 ns clk~clkctrl 2 COMB CLKCTRL_G6 33 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.293 ns; Loc. = CLKCTRL_G6; Fanout = 33; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 80 24 192 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.832 ns) + CELL(0.970 ns) 3.095 ns clk:inst6\|f500k 3 REG LCFF_X12_Y8_N29 3 " "Info: 3: + IC(0.832 ns) + CELL(0.970 ns) = 3.095 ns; Loc. = LCFF_X12_Y8_N29; Fanout = 3; REG Node = 'clk:inst6\|f500k'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.802 ns" { clk~clkctrl clk:inst6|f500k } "NODE_NAME" } } { "clk.v" "" { Text "E:/FPGA/work/spi3310/clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.178 ns) + CELL(0.000 ns) 5.273 ns clk:inst6\|f500k~clkctrl 4 COMB CLKCTRL_G5 59 " "Info: 4: + IC(2.178 ns) + CELL(0.000 ns) = 5.273 ns; Loc. = CLKCTRL_G5; Fanout = 59; COMB Node = 'clk:inst6\|f500k~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.178 ns" { clk:inst6|f500k clk:inst6|f500k~clkctrl } "NODE_NAME" } } { "clk.v" "" { Text "E:/FPGA/work/spi3310/clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.666 ns) 6.793 ns main:inst\|data_out\[7\] 5 REG LCFF_X18_Y11_N23 2 " "Info: 5: + IC(0.854 ns) + CELL(0.666 ns) = 6.793 ns; Loc. = LCFF_X18_Y11_N23; Fanout = 2; REG Node = 'main:inst\|data_out\[7\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.520 ns" { clk:inst6|f500k~clkctrl main:inst|data_out[7] } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 278 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.786 ns ( 41.01 % ) " "Info: Total cell delay = 2.786 ns ( 41.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.007 ns ( 58.99 % ) " "Info: Total interconnect delay = 4.007 ns ( 58.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.793 ns" { clk clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|data_out[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.793 ns" { clk clk~combout clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|data_out[7] } { 0.000ns 0.000ns 0.143ns 0.832ns 2.178ns 0.854ns } { 0.000ns 1.150ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.795 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.795 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns clk 1 CLK PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 80 24 192 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.293 ns clk~clkctrl 2 COMB CLKCTRL_G6 33 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.293 ns; Loc. = CLKCTRL_G6; Fanout = 33; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 80 24 192 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.832 ns) + CELL(0.970 ns) 3.095 ns clk:inst6\|f500k 3 REG LCFF_X12_Y8_N29 3 " "Info: 3: + IC(0.832 ns) + CELL(0.970 ns) = 3.095 ns; Loc. = LCFF_X12_Y8_N29; Fanout = 3; REG Node = 'clk:inst6\|f500k'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.802 ns" { clk~clkctrl clk:inst6|f500k } "NODE_NAME" } } { "clk.v" "" { Text "E:/FPGA/work/spi3310/clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.178 ns) + CELL(0.000 ns) 5.273 ns clk:inst6\|f500k~clkctrl 4 COMB CLKCTRL_G5 59 " "Info: 4: + IC(2.178 ns) + CELL(0.000 ns) = 5.273 ns; Loc. = CLKCTRL_G5; Fanout = 59; COMB Node = 'clk:inst6\|f500k~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.178 ns" { clk:inst6|f500k clk:inst6|f500k~clkctrl } "NODE_NAME" } } { "clk.v" "" { Text "E:/FPGA/work/spi3310/clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.666 ns) 6.795 ns main:inst\|i\[6\] 5 REG LCFF_X19_Y11_N23 19 " "Info: 5: + IC(0.856 ns) + CELL(0.666 ns) = 6.795 ns; Loc. = LCFF_X19_Y11_N23; Fanout = 19; REG Node = 'main:inst\|i\[6\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.522 ns" { clk:inst6|f500k~clkctrl main:inst|i[6] } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.786 ns ( 41.00 % ) " "Info: Total cell delay = 2.786 ns ( 41.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.009 ns ( 59.00 % ) " "Info: Total interconnect delay = 4.009 ns ( 59.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.795 ns" { clk clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|i[6] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.795 ns" { clk clk~combout clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|i[6] } { 0.000ns 0.000ns 0.143ns 0.832ns 2.178ns 0.856ns } { 0.000ns 1.150ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.793 ns" { clk clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|data_out[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.793 ns" { clk clk~combout clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|data_out[7] } { 0.000ns 0.000ns 0.143ns 0.832ns 2.178ns 0.854ns } { 0.000ns 1.150ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.795 ns" { clk clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|i[6] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.795 ns" { clk clk~combout clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|i[6] } { 0.000ns 0.000ns 0.143ns 0.832ns 2.178ns 0.856ns } { 0.000ns 1.150ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 278 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.145 ns" { main:inst|i[6] main:inst|LessThan13~157 main:inst|LessThan13~159 main:inst|Selector7~214 main:inst|Selector28~40 main:inst|Selector32~46 main:inst|Selector26~18 main:inst|WideNor0~61 main:inst|WideOr22 main:inst|Selector21~10 main:inst|data_out[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "9.145 ns" { main:inst|i[6] main:inst|LessThan13~157 main:inst|LessThan13~159 main:inst|Selector7~214 main:inst|Selector28~40 main:inst|Selector32~46 main:inst|Selector26~18 main:inst|WideNor0~61 main:inst|WideOr22 main:inst|Selector21~10 main:inst|data_out[7] } { 0.000ns 0.789ns 1.103ns 0.407ns 0.381ns 0.391ns 0.384ns 0.373ns 0.397ns 1.085ns 0.000ns } { 0.000ns 0.647ns 0.615ns 0.614ns 0.544ns 0.370ns 0.206ns 0.206ns 0.319ns 0.206ns 0.108ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.793 ns" { clk clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|data_out[7] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.793 ns" { clk clk~combout clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|data_out[7] } { 0.000ns 0.000ns 0.143ns 0.832ns 2.178ns 0.854ns } { 0.000ns 1.150ns 0.000ns 0.970ns 0.000ns 0.666ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.795 ns" { clk clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|i[6] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.795 ns" { clk clk~combout clk~clkctrl clk:inst6|f500k clk:inst6|f500k~clkctrl main:inst|i[6] } { 0.000ns 0.000ns 0.143ns 0.832ns 2.178ns 0.856ns } { 0.000ns 1.150ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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