spi3310.hier_info

FPGA模拟SPI接口驱动3310液晶屏的 详细驱动

|Block1
rst_out <= main:inst.rst_out
clk => clk:inst6.f40m
ce <= inst5.DB_MAX_OUTPUT_PORT_TYPE
sck <= spi3310:inst1.sck
mosi <= spi3310:inst1.mosi
dc <= spi3310:inst1.lcd_dc


|Block1|main:inst
clk => i[9].CLK
clk => i[8].CLK
clk => i[7].CLK
clk => i[6].CLK
clk => i[5].CLK
clk => i[4].CLK
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => data_out[7]~reg0.CLK
clk => data_out[6]~reg0.CLK
clk => data_out[5]~reg0.CLK
clk => data_out[4]~reg0.CLK
clk => data_out[3]~reg0.CLK
clk => data_out[2]~reg0.CLK
clk => data_out[1]~reg0.CLK
clk => data_out[0]~reg0.CLK
clk => en_out~reg0.CLK
clk => ce_out~reg0.CLK
clk => rst_out~reg0.CLK
clk => cmd_out~reg0.CLK
clk => current_state~0.IN1
rst => i[9].ACLR
rst => i[8].ACLR
rst => i[7].ACLR
rst => i[6].ACLR
rst => i[5].ACLR
rst => i[4].ACLR
rst => i[3].ACLR
rst => i[2].ACLR
rst => i[1].ACLR
rst => i[0].ACLR
rst => current_state~1.IN1
en_out <= en_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rst_out <= rst_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
ce_out <= ce_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
cmd_out <= cmd_out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Block1|clk:inst6
reset => f500k~1.OUTPUTSELECT
reset => j~32.OUTPUTSELECT
reset => j~33.OUTPUTSELECT
reset => j~34.OUTPUTSELECT
reset => j~35.OUTPUTSELECT
reset => j~36.OUTPUTSELECT
reset => j~37.OUTPUTSELECT
reset => j~38.OUTPUTSELECT
reset => j~39.OUTPUTSELECT
reset => j~40.OUTPUTSELECT
reset => j~41.OUTPUTSELECT
reset => j~42.OUTPUTSELECT
reset => j~43.OUTPUTSELECT
reset => j~44.OUTPUTSELECT
reset => j~45.OUTPUTSELECT
reset => j~46.OUTPUTSELECT
reset => j~47.OUTPUTSELECT
reset => j~48.OUTPUTSELECT
reset => j~49.OUTPUTSELECT
reset => j~50.OUTPUTSELECT
reset => j~51.OUTPUTSELECT
reset => j~52.OUTPUTSELECT
reset => j~53.OUTPUTSELECT
reset => j~54.OUTPUTSELECT
reset => j~55.OUTPUTSELECT
reset => j~56.OUTPUTSELECT
reset => j~57.OUTPUTSELECT
reset => j~58.OUTPUTSELECT
reset => j~59.OUTPUTSELECT
reset => j~60.OUTPUTSELECT
reset => j~61.OUTPUTSELECT
reset => j~62.OUTPUTSELECT
reset => j~63.OUTPUTSELECT
f40m => j[31].CLK
f40m => j[30].CLK
f40m => j[29].CLK
f40m => j[28].CLK
f40m => j[27].CLK
f40m => j[26].CLK
f40m => j[25].CLK
f40m => j[24].CLK
f40m => j[23].CLK
f40m => j[22].CLK
f40m => j[21].CLK
f40m => j[20].CLK
f40m => j[19].CLK
f40m => j[18].CLK
f40m => j[17].CLK
f40m => j[16].CLK
f40m => j[15].CLK
f40m => j[14].CLK
f40m => j[13].CLK
f40m => j[12].CLK
f40m => j[11].CLK
f40m => j[10].CLK
f40m => j[9].CLK
f40m => j[8].CLK
f40m => j[7].CLK
f40m => j[6].CLK
f40m => j[5].CLK
f40m => j[4].CLK
f40m => j[3].CLK
f40m => j[2].CLK
f40m => j[1].CLK
f40m => j[0].CLK
f40m => f500k~reg0.CLK
f500k <= f500k~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Block1|spi3310:inst1
en => next_state.CE_L.DATAB
en => Selector0.IN2
clk => sck.DATAIN
clk => mosi~reg0.CLK
clk => lcd_dc~reg0.CLK
clk => lcd_ce~reg0.CLK
clk => current_state~0.IN1
data[0] => Selector2.IN10
data[1] => Selector2.IN9
data[2] => Selector2.IN8
data[3] => Selector2.IN7
data[4] => Selector2.IN6
data[5] => Selector2.IN5
data[6] => Selector2.IN4
data[7] => Selector2.IN3
cmd => Selector3.IN2
lcd_dc <= lcd_dc~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_ce <= lcd_ce~reg0.DB_MAX_OUTPUT_PORT_TYPE
mosi <= mosi~reg0.DB_MAX_OUTPUT_PORT_TYPE
sck <= clk.DB_MAX_OUTPUT_PORT_TYPE