📄 spi3310.map.qmsg

📁 FPGA模拟SPI接口驱动3310液晶屏的详细驱动
💻 QMSG
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk clk:inst6 " "Info: Elaborating entity \"clk\" for hierarchy \"clk:inst6\"" {  } { { "Block1.bdf" "inst6" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 40 192 288 136 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi3310 spi3310:inst1 " "Info: Elaborating entity \"spi3310\" for hierarchy \"spi3310:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 160 528 664 288 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|Block1\|spi3310:inst1\|current_state 12 " "Info: State machine \"\|Block1\|spi3310:inst1\|current_state\" contains 12 states" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|Block1\|main:inst\|current_state 25 " "Info: State machine \"\|Block1\|main:inst\|current_state\" contains 25 states" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Block1\|spi3310:inst1\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|Block1\|spi3310:inst1\|current_state\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Block1\|spi3310:inst1\|current_state " "Info: Encoding result for state machine \"\|Block1\|spi3310:inst1\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "12 " "Info: Completed encoding using 12 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.Idle " "Info: Encoded state bit \"spi3310:inst1\|current_state.Idle\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.CE_L " "Info: Encoded state bit \"spi3310:inst1\|current_state.CE_L\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.DC " "Info: Encoded state bit \"spi3310:inst1\|current_state.DC\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.s0 " "Info: Encoded state bit \"spi3310:inst1\|current_state.s0\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.s1 " "Info: Encoded state bit \"spi3310:inst1\|current_state.s1\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.s2 " "Info: Encoded state bit \"spi3310:inst1\|current_state.s2\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.s3 " "Info: Encoded state bit \"spi3310:inst1\|current_state.s3\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.s4 " "Info: Encoded state bit \"spi3310:inst1\|current_state.s4\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.s5 " "Info: Encoded state bit \"spi3310:inst1\|current_state.s5\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.s6 " "Info: Encoded state bit \"spi3310:inst1\|current_state.s6\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.s7 " "Info: Encoded state bit \"spi3310:inst1\|current_state.s7\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "spi3310:inst1\|current_state.CE_H " "Info: Encoded state bit \"spi3310:inst1\|current_state.CE_H\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.CE_H 000000000000 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.CE_H\" uses code string \"000000000000\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.s7 000000000011 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.s7\" uses code string \"000000000011\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.s6 000000000101 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.s6\" uses code string \"000000000101\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.s5 000000001001 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.s5\" uses code string \"000000001001\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.s4 000000010001 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.s4\" uses code string \"000000010001\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.s3 000000100001 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.s3\" uses code string \"000000100001\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.s2 000001000001 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.s2\" uses code string \"000001000001\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.s1 000010000001 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.s1\" uses code string \"000010000001\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.s0 000100000001 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.s0\" uses code string \"000100000001\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.DC 001000000001 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.DC\" uses code string \"001000000001\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.CE_L 010000000001 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.CE_L\" uses code string \"010000000001\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|spi3310:inst1\|current_state.Idle 100000000001 " "Info: State \"\|Block1\|spi3310:inst1\|current_state.Idle\" uses code string \"100000000001\"" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|Block1\|main:inst\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|Block1\|main:inst\|current_state\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|Block1\|main:inst\|current_state " "Info: Encoding result for state machine \"\|Block1\|main:inst\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "25 " "Info: Completed encoding using 25 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.rst_L " "Info: Encoded state bit \"main:inst\|current_state.rst_L\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.rst_H " "Info: Encoded state bit \"main:inst\|current_state.rst_H\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.ce_L " "Info: Encoded state bit \"main:inst\|current_state.ce_L\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.ce_H " "Info: Encoded state bit \"main:inst\|current_state.ce_H\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.s1 " "Info: Encoded state bit \"main:inst\|current_state.s1\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.s2 " "Info: Encoded state bit \"main:inst\|current_state.s2\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.s3 " "Info: Encoded state bit \"main:inst\|current_state.s3\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.s4 " "Info: Encoded state bit \"main:inst\|current_state.s4\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.s5 " "Info: Encoded state bit \"main:inst\|current_state.s5\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.s6 " "Info: Encoded state bit \"main:inst\|current_state.s6\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.s7 " "Info: Encoded state bit \"main:inst\|current_state.s7\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.s8 " "Info: Encoded state bit \"main:inst\|current_state.s8\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.s9 " "Info: Encoded state bit \"main:inst\|current_state.s9\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.d0 " "Info: Encoded state bit \"main:inst\|current_state.d0\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.d1 " "Info: Encoded state bit \"main:inst\|current_state.d1\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.d2 " "Info: Encoded state bit \"main:inst\|current_state.d2\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.d3 " "Info: Encoded state bit \"main:inst\|current_state.d3\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.d4 " "Info: Encoded state bit \"main:inst\|current_state.d4\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.d5 " "Info: Encoded state bit \"main:inst\|current_state.d5\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.d6 " "Info: Encoded state bit \"main:inst\|current_state.d6\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.d7 " "Info: Encoded state bit \"main:inst\|current_state.d7\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.d8 " "Info: Encoded state bit \"main:inst\|current_state.d8\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.d9 " "Info: Encoded state bit \"main:inst\|current_state.d9\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.Idle " "Info: Encoded state bit \"main:inst\|current_state.Idle\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "main:inst\|current_state.Empty " "Info: Encoded state bit \"main:inst\|current_state.Empty\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.Idle 0000000000000000000000000 " "Info: State \"\|Block1\|main:inst\|current_state.Idle\" uses code string \"0000000000000000000000000\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.d9 0000000000000000000000110 " "Info: State \"\|Block1\|main:inst\|current_state.d9\" uses code string \"0000000000000000000000110\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.d8 0000000000000000000001010 " "Info: State \"\|Block1\|main:inst\|current_state.d8\" uses code string \"0000000000000000000001010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.d7 0000000000000000000010010 " "Info: State \"\|Block1\|main:inst\|current_state.d7\" uses code string \"0000000000000000000010010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.d6 0000000000000000000100010 " "Info: State \"\|Block1\|main:inst\|current_state.d6\" uses code string \"0000000000000000000100010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.d5 0000000000000000001000010 " "Info: State \"\|Block1\|main:inst\|current_state.d5\" uses code string \"0000000000000000001000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.d4 0000000000000000010000010 " "Info: State \"\|Block1\|main:inst\|current_state.d4\" uses code string \"0000000000000000010000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.d3 0000000000000000100000010 " "Info: State \"\|Block1\|main:inst\|current_state.d3\" uses code string \"0000000000000000100000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.d2 0000000000000001000000010 " "Info: State \"\|Block1\|main:inst\|current_state.d2\" uses code string \"0000000000000001000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.d1 0000000000000010000000010 " "Info: State \"\|Block1\|main:inst\|current_state.d1\" uses code string \"0000000000000010000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.d0 0000000000000100000000010 " "Info: State \"\|Block1\|main:inst\|current_state.d0\" uses code string \"0000000000000100000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.s9 0000000000001000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.s9\" uses code string \"0000000000001000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.s8 0000000000010000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.s8\" uses code string \"0000000000010000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.s7 0000000000100000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.s7\" uses code string \"0000000000100000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.s6 0000000001000000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.s6\" uses code string \"0000000001000000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.s5 0000000010000000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.s5\" uses code string \"0000000010000000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.s4 0000000100000000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.s4\" uses code string \"0000000100000000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.s3 0000001000000000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.s3\" uses code string \"0000001000000000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.s2 0000010000000000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.s2\" uses code string \"0000010000000000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.s1 0000100000000000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.s1\" uses code string \"0000100000000000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.ce_H 0001000000000000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.ce_H\" uses code string \"0001000000000000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.ce_L 0010000000000000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.ce_L\" uses code string \"0010000000000000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.rst_H 0100000000000000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.rst_H\" uses code string \"0100000000000000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.rst_L 1000000000000000000000010 " "Info: State \"\|Block1\|main:inst\|current_state.rst_L\" uses code string \"1000000000000000000000010\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|Block1\|main:inst\|current_state.Empty 0000000000000000000000011 " "Info: State \"\|Block1\|main:inst\|current_state.Empty\" uses code string \"0000000000000000000000011\"" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "main:inst\|current_state.d7 data_in GND " "Warning: Reduced register \"main:inst\|current_state.d7\" with stuck data_in port to stuck value GND" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "main:inst\|current_state.d8 data_in GND " "Warning: Reduced register \"main:inst\|current_state.d8\" with stuck data_in port to stuck value GND" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "main:inst\|current_state.d9 data_in GND " "Warning: Reduced register \"main:inst\|current_state.d9\" with stuck data_in port to stuck value GND" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 15 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "233 " "Info: Implemented 233 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "227 " "Info: Implemented 227 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 26 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 26 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 22 18:18:42 2007 " "Info: Processing ended: Sat Dec 22 18:18:42 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/work/spi3310/spi3310.map.smsg " "Info: Generated suppressed messages file E:/FPGA/work/spi3310/spi3310.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}
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