spi3310.map.qmsg

FPGA模拟SPI接口驱动3310液晶屏的 详细驱动

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 22 18:18:37 2007 " "Info: Processing started: Sat Dec 22 18:18:37 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spi3310 -c spi3310 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spi3310 -c spi3310" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk " "Info: Found entity 1: clk" {  } { { "clk.v" "" { Text "E:/FPGA/work/spi3310/clk.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi3310.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file spi3310.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi3310 " "Info: Found entity 1: spi3310" {  } { { "spi3310.v" "" { Text "E:/FPGA/work/spi3310/spi3310.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "main.v(117) " "Warning (10268): Verilog HDL information at main.v(117): Always Construct contains both blocking and non-blocking assignments" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 117 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file main.v" { { "Info" "ISGN_ENTITY_NAME" "1 main " "Info: Found entity 1: main" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst5 " "Warning: Block or symbol \"NOT\" of instance \"inst5\" overlaps another block or symbol" {  } { { "Block1.bdf" "" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 336 768 816 368 "inst5" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "main main:inst " "Info: Elaborating entity \"main\" for hierarchy \"main:inst\"" {  } { { "Block1.bdf" "inst" { Schematic "E:/FPGA/work/spi3310/Block1.bdf" { { 176 208 344 304 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 main.v(29) " "Warning (10230): Verilog HDL assignment warning at main.v(29): truncated value with size 32 to match size of target (10)" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "i main.v(42) " "Warning (10235): Verilog HDL Always Construct warning at main.v(42): variable \"i\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 42 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "i main.v(45) " "Warning (10235): Verilog HDL Always Construct warning at main.v(45): variable \"i\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 45 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "i main.v(50) " "Warning (10235): Verilog HDL Always Construct warning at main.v(50): variable \"i\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 50 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "i main.v(54) " "Warning (10235): Verilog HDL Always Construct warning at main.v(54): variable \"i\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 54 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "i main.v(57) " "Warning (10235): Verilog HDL Always Construct warning at main.v(57): variable \"i\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 57 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}