spi3310.fit.qmsg

FPGA模拟SPI接口驱动3310液晶屏的 详细驱动

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.924 ns register register " "Info: Estimated most critical path is register to register delay of 9.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns main:inst\|i\[1\] 1 REG LAB_X19_Y11 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y11; Fanout = 15; REG Node = 'main:inst\|i\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { main:inst|i[1] } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.181 ns) + CELL(0.370 ns) 1.551 ns main:inst\|LessThan12~175 2 COMB LAB_X21_Y11 2 " "Info: 2: + IC(1.181 ns) + CELL(0.370 ns) = 1.551 ns; Loc. = LAB_X21_Y11; Fanout = 2; COMB Node = 'main:inst\|LessThan12~175'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.551 ns" { main:inst|i[1] main:inst|LessThan12~175 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.624 ns) 3.442 ns main:inst\|LessThan12~177 3 COMB LAB_X18_Y12 2 " "Info: 3: + IC(1.267 ns) + CELL(0.624 ns) = 3.442 ns; Loc. = LAB_X18_Y12; Fanout = 2; COMB Node = 'main:inst\|LessThan12~177'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.891 ns" { main:inst|LessThan12~175 main:inst|LessThan12~177 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.624 ns) 4.253 ns main:inst\|Selector7~214 4 COMB LAB_X18_Y12 4 " "Info: 4: + IC(0.187 ns) + CELL(0.624 ns) = 4.253 ns; Loc. = LAB_X18_Y12; Fanout = 4; COMB Node = 'main:inst\|Selector7~214'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.811 ns" { main:inst|LessThan12~177 main:inst|Selector7~214 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.202 ns) 5.060 ns main:inst\|Selector28~40 5 COMB LAB_X18_Y12 2 " "Info: 5: + IC(0.605 ns) + CELL(0.202 ns) = 5.060 ns; Loc. = LAB_X18_Y12; Fanout = 2; COMB Node = 'main:inst\|Selector28~40'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.807 ns" { main:inst|Selector7~214 main:inst|Selector28~40 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.646 ns) 5.866 ns main:inst\|Selector32~46 6 COMB LAB_X18_Y12 2 " "Info: 6: + IC(0.160 ns) + CELL(0.646 ns) = 5.866 ns; Loc. = LAB_X18_Y12; Fanout = 2; COMB Node = 'main:inst\|Selector32~46'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.806 ns" { main:inst|Selector28~40 main:inst|Selector32~46 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.647 ns) 6.673 ns main:inst\|Selector26~18 7 COMB LAB_X18_Y12 2 " "Info: 7: + IC(0.160 ns) + CELL(0.647 ns) = 6.673 ns; Loc. = LAB_X18_Y12; Fanout = 2; COMB Node = 'main:inst\|Selector26~18'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.807 ns" { main:inst|Selector32~46 main:inst|Selector26~18 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.646 ns) 7.479 ns main:inst\|WideNor0~61 8 COMB LAB_X18_Y12 4 " "Info: 8: + IC(0.160 ns) + CELL(0.646 ns) = 7.479 ns; Loc. = LAB_X18_Y12; Fanout = 4; COMB Node = 'main:inst\|WideNor0~61'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.806 ns" { main:inst|Selector26~18 main:inst|WideNor0~61 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.206 ns) 9.005 ns main:inst\|WideOr38 9 COMB LAB_X17_Y11 1 " "Info: 9: + IC(1.320 ns) + CELL(0.206 ns) = 9.005 ns; Loc. = LAB_X17_Y11; Fanout = 1; COMB Node = 'main:inst\|WideOr38'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.526 ns" { main:inst|WideNor0~61 main:inst|WideOr38 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 9.816 ns main:inst\|Selector30~22 10 COMB LAB_X17_Y11 1 " "Info: 10: + IC(0.441 ns) + CELL(0.370 ns) = 9.816 ns; Loc. = LAB_X17_Y11; Fanout = 1; COMB Node = 'main:inst\|Selector30~22'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.811 ns" { main:inst|WideOr38 main:inst|Selector30~22 } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 119 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.924 ns main:inst\|ce_out 11 REG LAB_X17_Y11 2 " "Info: 11: + IC(0.000 ns) + CELL(0.108 ns) = 9.924 ns; Loc. = LAB_X17_Y11; Fanout = 2; REG Node = 'main:inst\|ce_out'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { main:inst|Selector30~22 main:inst|ce_out } "NODE_NAME" } } { "main.v" "" { Text "E:/FPGA/work/spi3310/main.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.443 ns ( 44.77 % ) " "Info: Total cell delay = 4.443 ns ( 44.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.481 ns ( 55.23 % ) " "Info: Total interconnect delay = 5.481 ns ( 55.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.924 ns" { main:inst|i[1] main:inst|LessThan12~175 main:inst|LessThan12~177 main:inst|Selector7~214 main:inst|Selector28~40 main:inst|Selector32~46 main:inst|Selector26~18 main:inst|WideNor0~61 main:inst|WideOr38 main:inst|Selector30~22 main:inst|ce_out } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x28_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x28_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "rst_out 0 " "Info: Pin \"rst_out\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ce 0 " "Info: Pin \"ce\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sck 0 " "Info: Pin \"sck\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "mosi 0 " "Info: Pin \"mosi\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "dc 0 " "Info: Pin \"dc\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 22 18:18:54 2007 " "Info: Processing ended: Sat Dec 22 18:18:54 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/work/spi3310/spi3310.fit.smsg " "Info: Generated suppressed messages file E:/FPGA/work/spi3310/spi3310.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}