clk.v

来自「FPGA模拟SPI接口驱动3310液晶屏的 详细驱动」· Verilog 代码 · 共 23 行

module clk (reset,f40m,f500k);
	input f40m,reset;
	output f500k;
	reg f500k;
	reg [31:0] j;
		always @(posedge f40m)
			if(reset)
				begin 
					f500k <= 0;
					j <= 0;
				end
			else
				begin
					if(j==40)
						begin
							j <= 0;
							f500k <= ~f500k;
						end
					else
						j <= j+1;
				end
endmodule