spi3310.sim.rpt

FPGA模拟SPI接口驱动3310液晶屏的 详细驱动

; |Block1|main:inst|LessThan1~83                ; |Block1|main:inst|LessThan1~83                ; combout          ;
; |Block1|main:inst|Selector10~102              ; |Block1|main:inst|Selector10~102              ; combout          ;
; |Block1|main:inst|i[0]                        ; |Block1|main:inst|i[0]                        ; regout           ;
; |Block1|main:inst|LessThan10~153              ; |Block1|main:inst|LessThan10~153              ; combout          ;
; |Block1|main:inst|LessThan10~154              ; |Block1|main:inst|LessThan10~154              ; combout          ;
; |Block1|main:inst|current_state.s2            ; |Block1|main:inst|current_state.s2            ; regout           ;
; |Block1|main:inst|LessThan3~100               ; |Block1|main:inst|LessThan3~100               ; combout          ;
; |Block1|main:inst|LessThan4~98                ; |Block1|main:inst|LessThan4~98                ; combout          ;
; |Block1|main:inst|LessThan4~99                ; |Block1|main:inst|LessThan4~99                ; combout          ;
; |Block1|main:inst|Selector7~149               ; |Block1|main:inst|Selector7~149               ; combout          ;
; |Block1|main:inst|Selector20~891              ; |Block1|main:inst|Selector20~891              ; combout          ;
; |Block1|main:inst|Selector17~76               ; |Block1|main:inst|Selector17~76               ; combout          ;
; |Block1|main:inst|current_state.s1            ; |Block1|main:inst|current_state.s1            ; regout           ;
; |Block1|main:inst|LessThan10~156              ; |Block1|main:inst|LessThan10~156              ; combout          ;
; |Block1|main:inst|LessThan2~140               ; |Block1|main:inst|LessThan2~140               ; combout          ;
; |Block1|main:inst|Selector8~144               ; |Block1|main:inst|Selector8~144               ; combout          ;
; |Block1|main:inst|WideOr30~19                 ; |Block1|main:inst|WideOr30~19                 ; combout          ;
; |Block1|main:inst|current_state.ce_H          ; |Block1|main:inst|current_state.ce_H          ; regout           ;
; |Block1|main:inst|WideOr30~20                 ; |Block1|main:inst|WideOr30~20                 ; combout          ;
; |Block1|main:inst|Selector6~132               ; |Block1|main:inst|Selector6~132               ; combout          ;
; |Block1|main:inst|WideOr30~21                 ; |Block1|main:inst|WideOr30~21                 ; combout          ;
; |Block1|main:inst|WideOr32                    ; |Block1|main:inst|WideOr32                    ; combout          ;
; |Block1|main:inst|Selector22~20               ; |Block1|main:inst|Selector22~20               ; combout          ;
; |Block1|main:inst|en_out                      ; |Block1|main:inst|en_out                      ; regout           ;
; |Block1|spi3310:inst1|current_state.Idle      ; |Block1|spi3310:inst1|current_state.Idle      ; regout           ;
; |Block1|spi3310:inst1|current_state.DC        ; |Block1|spi3310:inst1|current_state.DC        ; regout           ;
; |Block1|spi3310:inst1|Selector1~95            ; |Block1|spi3310:inst1|Selector1~95            ; combout          ;
; |Block1|spi3310:inst1|current_state.CE_H      ; |Block1|spi3310:inst1|current_state.CE_H      ; regout           ;
; |Block1|spi3310:inst1|Selector0~16            ; |Block1|spi3310:inst1|Selector0~16            ; combout          ;
; |Block1|spi3310:inst1|current_state.s7        ; |Block1|spi3310:inst1|current_state.s7        ; regout           ;
; |Block1|spi3310:inst1|current_state.CE_L      ; |Block1|spi3310:inst1|current_state.CE_L      ; regout           ;
; |Block1|spi3310:inst1|Selector1~96            ; |Block1|spi3310:inst1|Selector1~96            ; combout          ;
; |Block1|main:inst|current_state.rst_L         ; |Block1|main:inst|current_state.rst_L         ; regout           ;
; |Block1|main:inst|Selector11~32               ; |Block1|main:inst|Selector11~32               ; combout          ;
; |Block1|main:inst|WideOr13~66                 ; |Block1|main:inst|WideOr13~66                 ; combout          ;
; |Block1|main:inst|Selector21~8                ; |Block1|main:inst|Selector21~8                ; combout          ;
; |Block1|main:inst|data_out[3]                 ; |Block1|main:inst|data_out[3]                 ; regout           ;
; |Block1|spi3310:inst1|current_state.s2        ; |Block1|spi3310:inst1|current_state.s2        ; regout           ;
; |Block1|spi3310:inst1|current_state.s3        ; |Block1|spi3310:inst1|current_state.s3        ; regout           ;
; |Block1|spi3310:inst1|Selector2~95            ; |Block1|spi3310:inst1|Selector2~95            ; combout          ;
; |Block1|main:inst|data_out[6]                 ; |Block1|main:inst|data_out[6]                 ; regout           ;
; |Block1|spi3310:inst1|current_state.s4        ; |Block1|spi3310:inst1|current_state.s4        ; regout           ;
; |Block1|spi3310:inst1|current_state.s0        ; |Block1|spi3310:inst1|current_state.s0        ; regout           ;
; |Block1|spi3310:inst1|Selector2~96            ; |Block1|spi3310:inst1|Selector2~96            ; combout          ;
; |Block1|main:inst|data_out[0]                 ; |Block1|main:inst|data_out[0]                 ; regout           ;
; |Block1|main:inst|data_out[5]                 ; |Block1|main:inst|data_out[5]                 ; regout           ;
; |Block1|spi3310:inst1|current_state.s1        ; |Block1|spi3310:inst1|current_state.s1        ; regout           ;
; |Block1|spi3310:inst1|current_state.s6        ; |Block1|spi3310:inst1|current_state.s6        ; regout           ;
; |Block1|spi3310:inst1|Selector2~97            ; |Block1|spi3310:inst1|Selector2~97            ; combout          ;
; |Block1|spi3310:inst1|Selector2~98            ; |Block1|spi3310:inst1|Selector2~98            ; combout          ;
; |Block1|spi3310:inst1|current_state.s5        ; |Block1|spi3310:inst1|current_state.s5        ; regout           ;
; |Block1|main:inst|data_out[7]                 ; |Block1|main:inst|data_out[7]                 ; regout           ;
; |Block1|spi3310:inst1|Selector2~99            ; |Block1|spi3310:inst1|Selector2~99            ; combout          ;
; |Block1|spi3310:inst1|Selector2~100           ; |Block1|spi3310:inst1|Selector2~100           ; combout          ;
; |Block1|spi3310:inst1|Selector3~102           ; |Block1|spi3310:inst1|Selector3~102           ; combout          ;
; |Block1|main:inst|i[1]~40                     ; |Block1|main:inst|i[1]~40                     ; combout          ;
; |Block1|main:inst|i[1]~40                     ; |Block1|main:inst|i[1]~418                    ; cout             ;
; |Block1|main:inst|i[2]~41                     ; |Block1|main:inst|i[2]~41                     ; combout          ;
; |Block1|main:inst|i[2]~41                     ; |Block1|main:inst|i[2]~419                    ; cout             ;
; |Block1|main:inst|i[3]~39                     ; |Block1|main:inst|i[3]~39                     ; combout          ;
; |Block1|main:inst|i[3]~39                     ; |Block1|main:inst|i[3]~420                    ; cout             ;
; |Block1|main:inst|i[4]~34                     ; |Block1|main:inst|i[4]~34                     ; combout          ;
; |Block1|main:inst|i[4]~34                     ; |Block1|main:inst|i[4]~421                    ; cout             ;
; |Block1|main:inst|i[5]~35                     ; |Block1|main:inst|i[5]~35                     ; combout          ;
; |Block1|main:inst|i[5]~35                     ; |Block1|main:inst|i[5]~422                    ; cout             ;
; |Block1|main:inst|i[6]~36                     ; |Block1|main:inst|i[6]~36                     ; combout          ;
; |Block1|main:inst|Selector9~84                ; |Block1|main:inst|Selector9~84                ; combout          ;
; |Block1|main:inst|next_state.ce_H~57          ; |Block1|main:inst|next_state.ce_H~57          ; combout          ;
; |Block1|main:inst|Selector20~893              ; |Block1|main:inst|Selector20~893              ; combout          ;
; |Block1|main:inst|Selector20~897              ; |Block1|main:inst|Selector20~897              ; combout          ;
; |Block1|main:inst|Selector20~898              ; |Block1|main:inst|Selector20~898              ; combout          ;
; |Block1|main:inst|Selector20~899              ; |Block1|main:inst|Selector20~899              ; combout          ;
; |Block1|main:inst|Selector20~900              ; |Block1|main:inst|Selector20~900              ; combout          ;
; |Block1|main:inst|Selector20~902              ; |Block1|main:inst|Selector20~902              ; combout          ;
; |Block1|main:inst|Selector20~904              ; |Block1|main:inst|Selector20~904              ; combout          ;
; |Block1|main:inst|Selector20~906              ; |Block1|main:inst|Selector20~906              ; combout          ;
; |Block1|main:inst|Selector20~907              ; |Block1|main:inst|Selector20~907              ; combout          ;
; |Block1|main:inst|Selector20~908              ; |Block1|main:inst|Selector20~908              ; combout          ;
; |Block1|spi3310:inst1|next_state.CE_L~19      ; |Block1|spi3310:inst1|next_state.CE_L~19      ; combout          ;
; |Block1|main:inst|WideOr13~67                 ; |Block1|main:inst|WideOr13~67                 ; combout          ;
; |Block1|main:inst|Selector16~80               ; |Block1|main:inst|Selector16~80               ; combout          ;
; |Block1|main:inst|Selector19~72               ; |Block1|main:inst|Selector19~72               ; combout          ;
; |Block1|main:inst|Selector13~70               ; |Block1|main:inst|Selector13~70               ; combout          ;
; |Block1|main:inst|Selector17~78               ; |Block1|main:inst|Selector17~78               ; combout          ;
; |Block1|main:inst|Selector19~73               ; |Block1|main:inst|Selector19~73               ; combout          ;
; |Block1|main:inst|Selector14~71               ; |Block1|main:inst|Selector14~71               ; combout          ;
; |Block1|main:inst|Selector18~70               ; |Block1|main:inst|Selector18~70               ; combout          ;
; |Block1|main:inst|Selector12~69               ; |Block1|main:inst|Selector12~69               ; combout          ;
; |Block1|main:inst|LessThan0~79                ; |Block1|main:inst|LessThan0~79                ; combout          ;
; |Block1|main:inst|Selector15~62               ; |Block1|main:inst|Selector15~62               ; combout          ;
; |Block1|main:inst|i[0]~426                    ; |Block1|main:inst|i[0]~426                    ; combout          ;
; |Block1|spi3310:inst1|current_state.CE_H~17   ; |Block1|spi3310:inst1|current_state.CE_H~17   ; combout          ;
; |Block1|clk                                   ; |Block1|clk                                   ; combout          ;
; |Block1|rst_out                               ; |Block1|rst_out                               ; padio            ;
; |Block1|ce                                    ; |Block1|ce                                    ; padio            ;
; |Block1|sck                                   ; |Block1|sck                                   ; padio            ;
; |Block1|mosi                                  ; |Block1|mosi                                  ; padio            ;
; |Block1|clk~clkctrl                           ; |Block1|clk~clkctrl                           ; outclk           ;
; |Block1|spi3310:inst1|current_state.s2~feeder ; |Block1|spi3310:inst1|current_state.s2~feeder ; combout          ;
+-----------------------------------------------+-----------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                     ;
+---------------------------------------------+---------------------------------------------+------------------+
; Node Name                                   ; Output Port Name                            ; Output Port Type ;
+---------------------------------------------+---------------------------------------------+------------------+
; |Block1|spi3310:inst1|lcd_dc                ; |Block1|spi3310:inst1|lcd_dc                ; regout           ;
; |Block1|main:inst|i[6]                      ; |Block1|main:inst|i[6]                      ; regout           ;
; |Block1|main:inst|i[7]                      ; |Block1|main:inst|i[7]                      ; regout           ;
; |Block1|main:inst|i[8]                      ; |Block1|main:inst|i[8]                      ; regout           ;
; |Block1|main:inst|Selector20~887            ; |Block1|main:inst|Selector20~887            ; combout          ;
; |Block1|main:inst|Selector20~889            ; |Block1|main:inst|Selector20~889            ; combout          ;
; |Block1|main:inst|current_state.Empty       ; |Block1|main:inst|current_state.Empty       ; regout           ;
; |Block1|main:inst|current_state.s9          ; |Block1|main:inst|current_state.s9          ; regout           ;
; |Block1|main:inst|LessThan10~155            ; |Block1|main:inst|LessThan10~155            ; combout          ;
; |Block1|main:inst|Selector0~98              ; |Block1|main:inst|Selector0~98              ; combout          ;
; |Block1|main:inst|current_state.s7          ; |Block1|main:inst|current_state.s7          ; regout           ;
; |Block1|main:inst|LessThan8~112             ; |Block1|main:inst|LessThan8~112             ; combout          ;
; |Block1|main:inst|LessThan9~101             ; |Block1|main:inst|LessThan9~101             ; combout          ;
; |Block1|main:inst|Selector20~890            ; |Block1|main:inst|Selector20~890            ; combout          ;
; |Block1|main:inst|LessThan8~113             ; |Block1|main:inst|LessThan8~113             ; combout          ;
; |Block1|main:inst|current_state.s8          ; |Block1|main:inst|current_state.s8          ; regout           ;