spi3310.map.rpt

FPGA模拟SPI接口驱动3310液晶屏的 详细驱动

+---------------------+---------------------+---------------------+--------------------+--------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+---------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 92    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: main:inst ;
+----------------+----------+----------------------------+
; Parameter Name ; Value    ; Type                       ;
+----------------+----------+----------------------------+
; Idle           ; 00000000 ; Binary                     ;
; Empty          ; 01100100 ; Binary                     ;
; rst_L          ; 00001010 ; Binary                     ;
; rst_H          ; 00001011 ; Binary                     ;
; ce_L           ; 00001100 ; Binary                     ;
; ce_H           ; 00001101 ; Binary                     ;
; s1             ; 00000001 ; Binary                     ;
; s2             ; 00000010 ; Binary                     ;
; s3             ; 00000011 ; Binary                     ;
; s4             ; 00000100 ; Binary                     ;
; s5             ; 00000101 ; Binary                     ;
; s6             ; 00000110 ; Binary                     ;
; s7             ; 00000111 ; Binary                     ;
; s8             ; 00001000 ; Binary                     ;
; s9             ; 00001001 ; Binary                     ;
; d0             ; 00010100 ; Binary                     ;
; d1             ; 00010101 ; Binary                     ;
; d2             ; 00010110 ; Binary                     ;
; d3             ; 00010111 ; Binary                     ;
; d4             ; 00011000 ; Binary                     ;
; d5             ; 00011001 ; Binary                     ;
; d6             ; 00011010 ; Binary                     ;
; d7             ; 00011011 ; Binary                     ;
; d8             ; 00011100 ; Binary                     ;
; d9             ; 00011101 ; Binary                     ;
+----------------+----------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------+
; Parameter Settings for User Entity Instance: spi3310:inst1 ;
+----------------+----------+--------------------------------+
; Parameter Name ; Value    ; Type                           ;
+----------------+----------+--------------------------------+
; Idle           ; 00000000 ; Binary                         ;
; CE_L           ; 00000001 ; Binary                         ;
; DC             ; 00000010 ; Binary                         ;
; s0             ; 00000011 ; Binary                         ;
; s1             ; 00000100 ; Binary                         ;
; s2             ; 00000101 ; Binary                         ;
; s3             ; 00000110 ; Binary                         ;
; s4             ; 00000111 ; Binary                         ;
; s5             ; 00001000 ; Binary                         ;
; s6             ; 00001001 ; Binary                         ;
; s7             ; 00001010 ; Binary                         ;
; CE_H           ; 00001011 ; Binary                         ;
+----------------+----------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Dec 22 18:18:37 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spi3310 -c spi3310
Info: Found 1 design units, including 1 entities, in source file clk.v
    Info: Found entity 1: clk
Info: Found 1 design units, including 1 entities, in source file spi3310.v
    Info: Found entity 1: spi3310
Info: Found 1 design units, including 1 entities, in source file main.v
    Info: Found entity 1: main
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Elaborating entity "Block1" for the top level hierarchy
Warning: Block or symbol "NOT" of instance "inst5" overlaps another block or symbol
Info: Elaborating entity "main" for hierarchy "main:inst"
Warning (10230): Verilog HDL assignment warning at main.v(29): truncated value with size 32 to match size of target (10)
Warning (10235): Verilog HDL Always Construct warning at main.v(42): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(45): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(50): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(54): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(57): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(60): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(63): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(66): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(69): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(72): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(75): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(78): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(81): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(84): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(87): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(90): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at main.v(93): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control