spi3310.v

FPGA模拟SPI接口驱动3310液晶屏的 详细驱动

module spi3310(en, clk, data, cmd, lcd_dc, lcd_ce, mosi, sck);
input clk, cmd, en;
input [7:0] data;
output lcd_dc, lcd_ce, mosi, sck;

reg lcd_dc, lcd_ce, mosi;

assign sck=clk;

parameter 	Idle=8'd0,
			CE_L=8'd1, DC=8'd2, 
			s0=8'd3, s1=8'd4, s2=8'd5, s3=8'd6, s4=8'd7, s5=8'd8, s6=8'd9, s7=8'd10,
			CE_H=8'd11;

reg[7:0] current_state;
reg[7:0] next_state;

//状态机
//第一个进程
always @(posedge clk) 
begin
	current_state <= next_state;
end

//第二个进程
always @(current_state or en)
begin    
    next_state = Idle;
	case(current_state)
    Idle: 
		if(en)
			next_state = CE_L;
		else
			next_state = Idle;
			
	CE_L:
		next_state = DC;
	
	DC:
		next_state = s0;
	s0:
		next_state = s1;
	s1:
		next_state = s2;
	s2:
		next_state = s3;
	s3:
		next_state = s4;
	s4:
		next_state = s5;
	s5:
		next_state = s6;
	s6:
		next_state = s7;
	s7:
		next_state = CE_H;
	CE_H:
		next_state = Idle;  
	endcase
end 

//第三个进程，同步时序always模块，格式化描述次态寄存器输出
always @ (negedge clk)
begin
	case(next_state)
    Idle: 
		begin
		lcd_ce <= 1;
		mosi   <= 0;
		lcd_dc <= 0;
		end
			
	CE_L:
		//lcd_ce <= 1;
		mosi <= 0;
	
	DC:
		lcd_ce <= 1;
		
	s0:
		begin
		lcd_ce <= 0;
		if(cmd)
			lcd_dc <= 1;
		else
			lcd_dc <= 0;
		mosi <= data[7];
		end
	s1:
		mosi <= data[6];
	s2:
		mosi <= data[5];
	s3:
		mosi <= data[4];
	s4:
		mosi <= data[3];
	s5:
		mosi <= data[2];
	s6:
		mosi <= data[1];
	s7:
		begin
		mosi <= data[0];
		end
	CE_H:
		lcd_ce <= 1; 
	endcase	
end			

endmodule