spi3310.tan.rpt

FPGA模拟SPI接口驱动3310液晶屏的 详细驱动

; N/A                                     ; 153.05 MHz ( period = 6.534 ns )                    ; main:inst|current_state.d3 ; main:inst|data_out[7] ; clk        ; clk      ; None                        ; None                      ; 6.267 ns                ;
; N/A                                     ; 153.05 MHz ( period = 6.534 ns )                    ; main:inst|current_state.d3 ; main:inst|data_out[6] ; clk        ; clk      ; None                        ; None                      ; 6.267 ns                ;
; N/A                                     ; 153.54 MHz ( period = 6.513 ns )                    ; main:inst|current_state.d3 ; main:inst|data_out[3] ; clk        ; clk      ; None                        ; None                      ; 6.247 ns                ;
; N/A                                     ; 153.56 MHz ( period = 6.512 ns )                    ; main:inst|current_state.d3 ; main:inst|data_out[5] ; clk        ; clk      ; None                        ; None                      ; 6.246 ns                ;
; N/A                                     ; 153.59 MHz ( period = 6.511 ns )                    ; main:inst|current_state.d3 ; main:inst|data_out[1] ; clk        ; clk      ; None                        ; None                      ; 6.245 ns                ;
; N/A                                     ; 154.01 MHz ( period = 6.493 ns )                    ; main:inst|current_state.d3 ; main:inst|data_out[0] ; clk        ; clk      ; None                        ; None                      ; 6.227 ns                ;
; N/A                                     ; 154.04 MHz ( period = 6.492 ns )                    ; main:inst|current_state.d3 ; main:inst|data_out[4] ; clk        ; clk      ; None                        ; None                      ; 6.226 ns                ;
; N/A                                     ; 154.20 MHz ( period = 6.485 ns )                    ; main:inst|current_state.d3 ; main:inst|ce_out      ; clk        ; clk      ; None                        ; None                      ; 6.217 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                            ;                       ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------+
; tco                                                                             ;
+-------+--------------+------------+----------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From                 ; To      ; From Clock ;
+-------+--------------+------------+----------------------+---------+------------+
; N/A   ; None         ; 13.938 ns  ; main:inst|ce_out     ; ce      ; clk        ;
; N/A   ; None         ; 13.309 ns  ; spi3310:inst1|lcd_ce ; ce      ; clk        ;
; N/A   ; None         ; 12.400 ns  ; main:inst|rst_out    ; rst_out ; clk        ;
; N/A   ; None         ; 12.353 ns  ; spi3310:inst1|mosi   ; mosi    ; clk        ;
; N/A   ; None         ; 12.284 ns  ; spi3310:inst1|lcd_dc ; dc      ; clk        ;
; N/A   ; None         ; 8.293 ns   ; clk:inst6|f500k      ; sck     ; clk        ;
+-------+--------------+------------+----------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Dec 22 18:19:03 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off spi3310 -c spi3310 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk:inst6|f500k" as buffer
Info: Clock "clk" has Internal fmax of 106.26 MHz between source register "main:inst|i[6]" and destination register "main:inst|data_out[7]" (period= 9.411 ns)
    Info: + Longest register to register delay is 9.145 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y11_N23; Fanout = 19; REG Node = 'main:inst|i[6]'
        Info: 2: + IC(0.789 ns) + CELL(0.647 ns) = 1.436 ns; Loc. = LCCOMB_X19_Y11_N4; Fanout = 3; COMB Node = 'main:inst|LessThan13~157'
        Info: 3: + IC(1.103 ns) + CELL(0.615 ns) = 3.154 ns; Loc. = LCCOMB_X18_Y12_N12; Fanout = 2; COMB Node = 'main:inst|LessThan13~159'
        Info: 4: + IC(0.407 ns) + CELL(0.614 ns) = 4.175 ns; Loc. = LCCOMB_X18_Y12_N18; Fanout = 4; COMB Node = 'main:inst|Selector7~214'
        Info: 5: + IC(0.381 ns) + CELL(0.544 ns) = 5.100 ns; Loc. = LCCOMB_X18_Y12_N20; Fanout = 2; COMB Node = 'main:inst|Selector28~40'
        Info: 6: + IC(0.391 ns) + CELL(0.370 ns) = 5.861 ns; Loc. = LCCOMB_X18_Y12_N0; Fanout = 2; COMB Node = 'main:inst|Selector32~46'
        Info: 7: + IC(0.384 ns) + CELL(0.206 ns) = 6.451 ns; Loc. = LCCOMB_X18_Y12_N30; Fanout = 2; COMB Node = 'main:inst|Selector26~18'
        Info: 8: + IC(0.373 ns) + CELL(0.206 ns) = 7.030 ns; Loc. = LCCOMB_X18_Y12_N24; Fanout = 4; COMB Node = 'main:inst|WideNor0~61'
        Info: 9: + IC(0.397 ns) + CELL(0.319 ns) = 7.746 ns; Loc. = LCCOMB_X18_Y12_N8; Fanout = 9; COMB Node = 'main:inst|WideOr22'
        Info: 10: + IC(1.085 ns) + CELL(0.206 ns) = 9.037 ns; Loc. = LCCOMB_X18_Y11_N22; Fanout = 1; COMB Node = 'main:inst|Selector21~10'
        Info: 11: + IC(0.000 ns) + CELL(0.108 ns) = 9.145 ns; Loc. = LCFF_X18_Y11_N23; Fanout = 2; REG Node = 'main:inst|data_out[7]'
        Info: Total cell delay = 3.835 ns ( 41.94 % )
        Info: Total interconnect delay = 5.310 ns ( 58.06 % )
    Info: - Smallest clock skew is -0.002 ns
        Info: + Shortest clock path from clock "clk" to destination register is 6.793 ns
            Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.293 ns; Loc. = CLKCTRL_G6; Fanout = 33; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.832 ns) + CELL(0.970 ns) = 3.095 ns; Loc. = LCFF_X12_Y8_N29; Fanout = 3; REG Node = 'clk:inst6|f500k'
            Info: 4: + IC(2.178 ns) + CELL(0.000 ns) = 5.273 ns; Loc. = CLKCTRL_G5; Fanout = 59; COMB Node = 'clk:inst6|f500k~clkctrl'
            Info: 5: + IC(0.854 ns) + CELL(0.666 ns) = 6.793 ns; Loc. = LCFF_X18_Y11_N23; Fanout = 2; REG Node = 'main:inst|data_out[7]'
            Info: Total cell delay = 2.786 ns ( 41.01 % )
            Info: Total interconnect delay = 4.007 ns ( 58.99 % )
        Info: - Longest clock path from clock "clk" to source register is 6.795 ns
            Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_132; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.293 ns; Loc. = CLKCTRL_G6; Fanout = 33; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.832 ns) + CELL(0.970 ns) = 3.095 ns; Loc. = LCFF_X12_Y8_N29; Fanout = 3; REG Node = 'clk:inst6|f500k'
            Info: 4: + IC(2.178 ns) + CELL(0.000 ns) = 5.273 ns; Loc.