📄 fdwt97_address_r.v
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end
else
Reg_RL = Reg_RL + 1;
end
//Write Memory Address
if(Address_OutW == 'h3FF) begin
Address_OutW = 'h3FF;
Delay = 0;
Clr = 1'b0;
End_B = 1'b1;
DWT97_Reset = 1'b0;
Chang_Mode = 1'b1;
Write_En = 1'b0;
end
else begin
Chang_Mode = 1'b0;
if(Delay == 16) begin //14
if(Flag) begin //if Flag == 1, ==> save Low Data
Address_OutW = {3'b000, Reg_WH[4:0], Reg_WL[3:0]};
Write_En = 1'b1;
Flag = ~Flag;
end // Flag == 1 ==> End
else begin //if Flag == 0, ==> save High Data
Write_En = 1'b1;
Address_OutW = {3'b001, Reg_WH[4:0], Reg_WL[3:0]};
if(Reg_WL[3:0] == 4'hF) begin //if HiPath == 31
Delay = 8; //6
End_B = 1'b1;
Flag = ~Flag;
end
else begin
Delay = 16;
End_B = 1'b0;
Flag = ~Flag;
end
if(Reg_WL[3:0] == ((Line_End>>2)-1)) begin
Reg_WH = Reg_WH + 1;
Write_En = 1'b1;
Reg_WL = 0;
end
else
Reg_WL = Reg_WL + 1;
end //Flag == 0 ==> End
end
else begin
Write_En = 1'b0;
Delay = Delay + 1;
Address_OutW = {3'b001, Reg_WH[4:0], Reg_WL[3:0]};
if(End_B)
End_B = ~End_B;
end
end
end //Address_OutW End
end//S3 End
S4: begin //2D-1Level
Level_Choose = S4;
Choose_RW = 1'b1;
if(!Clr) begin
Address_OutR = 0;
Address_OutW = 0;
Reg_WL = 0;
Reg_WH = 0;
Flag = 1; //LowPath
Reg_RH = 6;
Reg_RL = 0;
L_Boundary = 1'b1;
R_Boundary = 1'b0;
if(End_B) begin
End_B = ~End_B;
Clr = 1'b0;
end
else
Clr = 1;
DWT97_Reset = 1'b0;
Chang_Mode = 1'b0;
Delay_Mode = 1'b0;
Done = 1'b0;
Write_En = 1'b0;
LowPath = 1'b1; //LL-Path
HiPath = 1'b1; //Hi-Path
end
else begin
Clr = 1'b1;
DWT97_Reset = 1'b1;
if(LowPath)
Address_OutR = {3'b000, Reg_RH[4:0], Reg_RL[3:0]}; //Low Path
else
Address_OutR = {3'b001, Reg_RH[4:0], Reg_RL[3:0]}; //Hi Path
//Read Memory Address
if(L_Boundary) begin
if(Reg_RH == 0) begin
Reg_RH = Reg_RH + 1;
L_Boundary = 1'b0;
R_Boundary = 1'b0;
Delay_Mode = 1'b0;
end
else begin
if(Delay_Mode)
Delay_Mode = 1'b0;
Reg_RH = Reg_RH - 1;
L_Boundary = 1'b1;
R_Boundary = 1'b0;
end
end
else if(R_Boundary)begin
if(Address_OutR == 12'h3FF) begin
Address_OutR = 12'h3FF;
R_Boundary = 1'b1;
L_Boundary = 1'b0;
end
else begin
if(Reg_RH[4:0] == 5'h1C) begin
//Hi Path
if(LowPath) begin
LowPath = ~LowPath;
Reg_RH = 5;
R_Boundary = 1'b0;
L_Boundary = 1'b1;
Delay_Mode = 1'b0;
end
else begin
LowPath = ~LowPath;
Reg_RH = 5;
Reg_RL = Reg_RL + 1;
R_Boundary = 1'b0;
L_Boundary = 1'b1;
Delay_Mode = 1'b0;
end
end
else
Reg_RH = Reg_RH - 1;
R_Boundary = 1'b1;
end
end
else begin
Delay_Mode = 1'b0;
if(Reg_RH[4:0] == 5'h1F) begin
R_Boundary = 1'b1;
Reg_RH = Reg_RH - 1;
end
else
Reg_RH = Reg_RH + 1;
end
//Write Memory Address
if(Address_OutW == 'h3FF) begin
Address_OutW = 'h3FF;
Delay = 0;
DWT97_Reset = 1'b0;
End_B = 1'b1;
Clr = 1'b0;
Chang_Mode = 1'b1;
Write_En = 1'b0;
end
else begin
Chang_Mode = 1'b0;
if(Delay == 16) begin //14
if(Flag) begin //if Flag == 1, ==> save Low Data
if(HiPath) //Save Low Path
Address_OutW = {4'b0000, Reg_WH[3:0], Reg_WL[3:0]};
else
Address_OutW = {4'b0010, Reg_WH[3:0], Reg_WL[3:0]};
Write_En = 1'b1;
Flag = ~Flag;
end // Flag == 1 ==> End
else begin //if Flag == 0, ==> save High Data
Write_En = 1'b1;
if(HiPath)
Address_OutW = {4'b0001, Reg_WH[3:0], Reg_WL[3:0]};
else
Address_OutW = {4'b0011, Reg_WH[3:0], Reg_WL[3:0]};
if(Reg_WH[3:0] == 4'hF) begin //if HiPath == 15
Delay = 8; //6
End_B = 1'b1;
Flag = ~Flag;
end
else begin
Delay = 16;
End_B = 1'b0;
Flag = ~Flag;
end
if(Reg_WH[3:0] == 4'hF) begin
if(HiPath) begin
HiPath = ~HiPath;
Write_En = 1'b1;
Reg_WH = 0;
end
else begin
HiPath = ~HiPath;
Reg_WL = Reg_WL + 1;
Write_En = 1'b1;
Reg_WH = 0;
end
end
else
Reg_WH = Reg_WH + 1;
end //Flag == 0 ==> End
end
else begin
Write_En = 1'b0;
Delay = Delay + 1;
// if(End_B)
// End_B = ~End_B;
end
end
end //Address_OutW End
end//S4 End
S5: begin
Level_Choose = S5;
if(!Clr) begin
Address_OutR = 0;
Address_OutW = 0;
Reg_WL = 0;
Reg_WH = 0;
Flag = 1; //LowPath
Reg_RH = 0;
Reg_RL = 5;
L_Boundary = 1'b1;
R_Boundary = 1'b0;
if(End_B) begin
End_B = ~End_B;
Clr = 1'b0;
end
else
Clr = 1;
DWT97_Reset = 1'b0;
Chang_Mode = 1'b0;
Delay_Mode = 1'b0;
Done = 1'b0;
Write_En = 1'b0;
end
else begin
DWT97_Reset = 1'b1;
Clr = 1'b1;
Address_OutR = {4'h0, Reg_RH[3:0], Reg_RL[3:0]}; //31,31
//Read Memory Address
if(L_Boundary) begin
if(Reg_RL==0) begin
Reg_RL = Reg_RL + 1;
L_Boundary = 1'b0;
Delay_Mode = 1'b0;
end
else begin
if(Delay_Mode)
Delay_Mode = 1'b0;
Reg_RL = Reg_RL - 1;
L_Boundary = 1'b1;
end
end
else if(R_Boundary)begin
if({4'h0, Reg_RH[3:0], Reg_RL[3:0]} == 12'h0FF) begin
Reg_RL = 5'h0F;
Reg_RH = 5'h0F;
R_Boundary = 1'b1;
L_Boundary = 1'b0;
end
else begin
if(Reg_RL[3:0] == 4'hB) begin
Reg_RL = 4;
Reg_RH = Reg_RH + 1;
R_Boundary = 1'b0;
L_Boundary = 1'b1;
Delay_Mode = 1'b0;
end
else begin
Reg_RL = Reg_RL - 1;
R_Boundary = 1'b1;
L_Boundary = 1'b0;
Delay_Mode = 1'b0;
end
end
end
else begin
Delay_Mode = 1'b0;
if(Reg_RL[3:0] == 4'hF) begin
R_Boundary = 1'b1;
Reg_RL = Reg_RL - 1;
end
else
Reg_RL = Reg_RL + 1;
end
//Write Memory Address
if(Address_OutW == 'h0FF) begin
Address_OutW = 'h0FF;
Delay = 0;
Clr = 1'b0;
End_B = 1'b1;
DWT97_Reset = 1'b0;
Chang_Mode = 1'b1;
Write_En = 1'b0;
end
else begin
Chang_Mode = 1'b0;
if(Delay == 14) begin
if(Flag) begin //if Flag == 1, ==> save Low Data
Address_OutW = {5'h00, Reg_WH[3:0], Reg_WL[2:0]};
Write_En = 1'b1;
Flag = ~Flag;
end // Flag == 1 ==> End
else begin //if Flag == 0, ==> save High Data
Write_En = 1'b1;
Address_OutW = {5'h01, Reg_WH[3:0], Reg_WL[2:0]};
if(Reg_WL[3:0] == 4'hF) begin //if HiPath == 31
Delay = 6;
End_B = 1'b1;
Flag = ~Flag;
end
else begin
Delay = 14;
End_B = 1'b0;
Flag = ~Flag;
end
if(Reg_WL[2:0] == ((Line_End>>3)-1)) begin
Reg_WH = Reg_WH + 1;
Write_En = 1'b1;
Reg_WL = 0;
end
else
Reg_WL = Reg_WL + 1;
end //Flag == 0 ==> End
end
else begin
Write_En = 1'b0;
Delay = Delay + 1;
Address_OutW = {5'b001, Reg_WH[3:0], Reg_WL[2:0]};
end
end
end //Address_OutW End
end//S5 End
S6: begin //2D-1Level
Level_Choose = S6;
DWT97_Reset = 1'b1;
if(!Clr) begin
Address_OutR = 0;
Address_OutW = 0;
Reg_WL = 0;
Reg_WH = 0;
Flag = 1; //LowPath
Reg_RH = 5;
Reg_RL = 0;
L_Boundary = 1'b1;
R_Boundary = 1'b0;
if(End_B) begin
End_B = ~End_B;
Clr = 1'b0;
end
else
Clr = 1;
DWT97_Reset = 1'b0;
Chang_Mode = 1'b0;
Delay_Mode = 1'b0;
Done = 1'b0;
Write_En = 1'b0;
LowPath = 1'b1; //LL-Path
HiPath = 1'b1; //Hi-Path
end
else begin
Clr = 1'b1;
if(LowPath)
Address_OutR = {3'b000, Reg_RH[4:0], Reg_RL[3:0]}; //Low Path
else
Address_OutR = {3'b001, Reg_RH[4:0], Reg_RL[3:0]}; //Hi Path
//Read Memory Address
if(L_Boundary) begin
if(Reg_RH == 0) begin
Reg_RH = Reg_RH + 1;
L_Boundary = 1'b0;
R_Boundary = 1'b0;
Delay_Mode = 1'b0;
end
else begin
if(Delay_Mode)
Delay_Mode = 1'b0;
Reg_RH = Reg_RH - 1;
L_Boundary = 1'b1;
R_Boundary = 1'b0;
end
end
else if(R_Boundary)begin
if(Address_OutR == 12'h3FF) begin
Address_OutR = 12'h3FF;
R_Boundary = 1'b1;
L_Boundary = 1'b0;
end
else begin
if(Reg_RH[4:0] == 5'h1C) begin
//Hi Path
if(LowPath) begin
LowPath = ~LowPath;
Reg_RH = 5;
R_Boundary = 1'b0;
L_Boundary = 1'b1;
Delay_Mode = 1'b0;
end
else begin
LowPath = ~LowPath;
Reg_RH = 5;
Reg_RL = Reg_RL + 1;
R_Boundary = 1'b0;
L_Boundary = 1'b1;
Delay_Mode = 1'b0;
end
end
else
Reg_RH = Reg_RH - 1;
R_Boundary = 1'b1;
end
end
else begin
Delay_Mode = 1'b0;
if(Reg_RH[4:0] == 5'h1F) begin
R_Boundary = 1'b1;
Reg_RH = Reg_RH - 1;
end
else
Reg_RH = Reg_RH + 1;
end
//Write Memory Address
if(Address_OutW == 'h3FF) begin
Address_OutW = 'h3FF;
Delay = 0;
DWT97_Reset = 1'b0;
Chang_Mode = 1'b1;
Write_En = 1'b0;
end
else begin
Chang_Mode = 1'b0;
if(Delay == 14) begin
if(Flag) begin //if Flag == 1, ==> save Low Data
if(HiPath) //Save Low Path
Address_OutW = {4'b0000, Reg_WH[3:0], Reg_WL[3:0]};
else
Address_OutW = {4'b0010, Reg_WH[3:0], Reg_WL[3:0]};
Write_En = 1'b1;
Flag = ~Flag;
end // Flag == 1 ==> End
else begin //if Flag == 0, ==> save High Data
Write_En = 1'b1;
if(HiPath)
Address_OutW = {4'b0001, Reg_WH[3:0], Reg_WL[3:0]};
else
Address_OutW = {4'b0011, Reg_WH[3:0], Reg_WL[3:0]};
if(Reg_WH[3:0] == 4'hF) begin //if HiPath == 15
Delay = 6;
End_B = 1'b1;
Flag = ~Flag;
end
else begin
Delay = 14;
End_B = 1'b0;
Flag = ~Flag;
end
if(Reg_WH[3:0] == 4'hF) begin
if(HiPath) begin
HiPath = ~HiPath;
Write_En = 1'b1;
Reg_WH = 0;
end
else begin
HiPath = ~HiPath;
Reg_WL = Reg_WL + 1;
Write_En = 1'b1;
Reg_WH = 0;
end
end
else
Reg_WH = Reg_WH + 1;
end //Flag == 0 ==> End
end
else begin
Write_En = 1'b0;
Delay = Delay + 1;
if(End_B)
End_B = ~End_B;
end
end
end //Address_OutW End
end//S2 End
SEnd: begin
Address_OutR = 0;
Address_OutW = 0;
Reg_WL = 0;
Reg_WH = 0;
Flag = 0;
Reg_RH = 0;
Reg_RL = 2;
L_Boundary = 1'b1;
R_Boundary = 1'b0;
Clr = 1'b0;
DWT97_Reset = 1'b0;
Chang_Mode = 1'b0;
Level_Choose = SEnd;
Write_En = 1'b0;
Done = 1'b1;
End_B = 1'b0;
end//SEnd
endcase
end
endmodule⌨️ 快捷键说明
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