dual_ram_gdf.rpt

VHDL 源程序 开发环境：MAXPLUS II 10.2

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:    e:\max-plus-file\dual_ram_gdf\dual_ram_gdf.rpt
dual_ram_gdf

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  39     19    B     OUTPUT      t        0      0   0    4    0    0    0  P/Q
  28     28    B     OUTPUT      t        1      0   0   20    0    0    0  RAM_CE
  34     23    B     OUTPUT      t        0      0   0   13    0    0    0  SEM_OK


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:    e:\max-plus-file\dual_ram_gdf\dual_ram_gdf.rpt
dual_ram_gdf

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

               Logic cells placed in LAB 'B'
        +----- LC19 P/Q
        | +--- LC28 RAM_CE
        | | +- LC23 SEM_OK
        | | | 
        | | |   Other LABs fed by signals
        | | |   that feed LAB 'B'
LC      | | | | A B |     Logic cells that feed LAB 'B':

Pin
4    -> - * - | - * | <-- AEN
18   -> - * * | - * | <-- A0
19   -> - * * | - * | <-- A1
20   -> - * * | - * | <-- A2
14   -> - * * | - * | <-- A3
16   -> - * * | - * | <-- A4
17   -> - * * | - * | <-- A5
36   -> - * * | - * | <-- A6
37   -> - * * | - * | <-- A7
40   -> - * * | - * | <-- A8
41   -> - * * | - * | <-- A9
21   -> - * * | - * | <-- A10
26   -> - * * | - * | <-- A11
12   -> - * * | - * | <-- A12
11   -> * * - | - * | <-- A16
9    -> * * - | - * | <-- A17
8    -> * * - | - * | <-- A18
25   -> * * - | - * | <-- A19
6    -> - * - | - * | <-- IOR
5    -> - * - | - * | <-- IOW


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:    e:\max-plus-file\dual_ram_gdf\dual_ram_gdf.rpt
dual_ram_gdf

** EQUATIONS **

AEN      : INPUT;
A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
A4       : INPUT;
A5       : INPUT;
A6       : INPUT;
A7       : INPUT;
A8       : INPUT;
A9       : INPUT;
A10      : INPUT;
A11      : INPUT;
A12      : INPUT;
A16      : INPUT;
A17      : INPUT;
A18      : INPUT;
A19      : INPUT;
IOR      : INPUT;
IOW      : INPUT;

-- Node name is 'P/Q' 
-- Equation name is 'P/Q', location is LC019, type is output.
 P/Q     = LCELL( _EQ001 $  VCC);
  _EQ001 =  A16 & !A17 &  A18 &  A19;

-- Node name is 'RAM_CE' 
-- Equation name is 'RAM_CE', location is LC028, type is output.
 RAM_CE  = LCELL( _EQ002 $  _EQ003);
  _EQ002 = !AEN & !A0 & !A1 & !A2 & !A3 & !A4 & !A5 & !A6 & !A7 & !A8 & !A9 & 
             !A10 & !A11 &  A12 &  A16 & !A17 &  A18 &  A19 &  IOR &  IOW;
  _EQ003 =  _X001;
  _X001  = EXP(!AEN &  A16 & !A17 &  A18 &  A19 &  IOR &  IOW);

-- Node name is 'SEM_OK' 
-- Equation name is 'SEM_OK', location is LC023, type is output.
 SEM_OK  = LCELL( _EQ004 $  VCC);
  _EQ004 = !A0 & !A1 & !A2 & !A3 & !A4 & !A5 & !A6 & !A7 & !A8 & !A9 & !A10 & 
             !A11 &  A12;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information             e:\max-plus-file\dual_ram_gdf\dual_ram_gdf.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,068K