📄 sprm180.bsm
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MFSRA : inout bit;
MFSXA : inout bit;
MCLKRA : inout bit;
MCLKXA : inout bit;
CANRXA : inout bit;
CANTXA : inout bit;
SCIRXDA : inout bit;
SCITXDA : inout bit;
SPISTEA : inout bit;
SPICLKA : inout bit;
SPISOMIA : inout bit;
SPISIMOA : inout bit;
SCITXDB : inout bit;
SCIRXDB : inout bit;
TESTSEL : in bit;
X1_XCLKIN : linkage bit;
X2 : linkage bit;
XA : out bit_vector(18 downto 0);
XCLKOUT : out bit;
XD : inout bit_vector(15 downto 0);
XHOLDAn : out bit;
XHOLDn : in bit;
XMPnMC : in bit;
XRDn : out bit;
XREADY : in bit;
XRnW : out bit;
XRSn : inout bit;
XWEn : out bit;
XZCS0AND1n : out bit;
XZCS2n : out bit;
XZCS6AND7n : out bit;
TDI : in bit;
TMS : in bit;
TCK : in bit;
TDO : out bit;
TRSTn : in bit;
EMU0 : in bit;
EMU1 : in bit;
TEST1 : linkage bit;
TEST2 : linkage bit
);
use STD_1149_1_1994.all; -- Get IEEE 1149.1-1994 attributes and definitions
attribute COMPONENT_CONFORMANCE of TMS320F2812 : entity is "STD_1149_1_1993";
attribute PIN_MAP of TMS320F2812 : entity is PHYSICAL_PIN_MAP;
constant GHH : PIN_MAP_STRING :=
"VDDAIO:B2,"&
"VDDA1:F4,"&
"VSSA1:F3,"&
"VDD: (H1,L1,P5,P9,P12,K12,G12,C14,B10,C8)," &
"VSS: (G4,L2,P4,K6,P8,M10,L11,K13,J14,G13,E14,B14,D10,B8,C10,K1)," &
"VDDIO: (J4,L7,L10,N14,G11,E9)," &
"VDD3VFL:N8," &
"VDD1:A6," &
"VSS1:C6," &
"VDDA2:A5," &
"VSSA2:C5," &
"VSSAIO:A2," &
"ADCINA: (B5,D5,E5,A4,B4,C4,D4,A3)," &
"ADCINB: (F5,D1,D2,D3,C1,B1,C3,C2)," &
"ADCLO: B3," &
"ADCREFM: E4," &
"ADCREFP: E2," &
"ADCRESEXT: F2," &
"AVSSREFBG: E3," &
"AVDDREFBG:E1," &
"ADCBGREFIN: E6," &
"C3TRIPn: F10," &
"C2TRIPn: E11," &
"C1TRIPn: E13," &
"TCLKINA: F13," &
"TDIRA: F14," &
"CAP3_QEPI1: H12," &
"CAP2_QEP2: H11," &
"CAP1_QEP1: H10," &
"T2PWM_T2CMP: J13," &
"T1PWM_T1CMP: J11," &
"PWM6: K14," &
"PWM5: K11," &
"PWM4: L13," &
"PWM3: L12," &
"PWM2: M14," &
"PWM1: M12," &
"C6TRIPn: K7," &
"C5TRIPn: L6," &
"C4TRIPn: N6," &
"TCLKINB: K8," &
"TDIRB: L8," &
"CAP6_QEPI2: P6," &
"CAP5_QEP4: M6," &
"CAP4_QEP3: M5," &
"T4PWM_T4CMP: N5," &
"T3PWM_T3CMP: K5," &
"PWM12: M4," &
"PWM11: L4," &
"PWM10: P3," &
"PWM9: N3," &
"PWM8: P2," &
"PWM7: N2," &
"T1CTRIPn_PDPINTAn: H14," &
"T2CTRIPn_EVASOCn: G10," &
"T3CTRIPn_PDPINTBn: P10," &
"T4CTRIPn_EVBSOCn: P11," &
"XINT1_XBIOn: D9," &
"XINT2_ADCSOC: D8," &
"XNMI_XINT13: E8," &
"XF_XPLLDISn: A11," &
"MDRA: G2," &
"MDXA: G1," &
"MFSRA: J2," &
"MFSXA: H4," &
"MCLKRA: H2," &
"MCLKXA: J1," &
"CANRXA: N13," &
"CANTXA: N12," &
"SCIRXDA: A7," &
"SCITXDA: C7," &
"SPISTEA: K4," &
"SPICLKA: K2," &
"SPISOMIA: N1," &
"SPISIMOA: M1," &
"SCITXDB: P14," &
"SCIRXDB: M13," &
"TESTSEL: A13," &
"X1_XCLKIN: K9," &
"X2: M9," &
"XA: (D7,B7,A8,B9,A10,E10,C11,A14,C12,D14,E12,F12,G14,H13,J12,M11,N10,M2,G5)," &
"XCLKOUT: F11," &
"XD: (A9,B11,J10,L14,N9,L9,M8,P7,L5,L3,J5,K3,J3,H5,H3,G3)," &
"XHOLDAn: K10," &
"XHOLDn: E7," &
"XMPnMC: F1," &
"XRDn: M3," &
"XREADY: B6," &
"XRnW: N4," &
"XRSn: D6," &
"XWEn: N11," &
"XZCS0AND1n: P1," &
"XZCS2n: P13," &
"XZCS6AND7n: B13," &
"TDI: C13," &
"TMS: D13," &
"TCK: A12," &
"TDO: D12," &
"TRSTn: B12," &
"EMU0: D11," &
"EMU1: C9," &
"TEST1: M7 ," &
"TEST2: N7";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);
attribute TAP_SCAN_RESET of TRSTN : signal is true;
attribute COMPLIANCE_PATTERNS of TMS320F2812 : entity is "(TESTSEL,EMU1,EMU0)(001)";
attribute INSTRUCTION_LENGTH of TMS320F2812 : entity is 3;
attribute INSTRUCTION_OPCODE of TMS320F2812 : entity is
"extest (000)," &
"bypass (111)," &
"sample (001)," &
"idcode (100)";
attribute INSTRUCTION_CAPTURE of TMS320F2812 : entity is "001";
attribute IDCODE_REGISTER of TMS320F2812 : entity is
"0001" & -- Version Number
"1011010011110100" & -- Part Number
"00000010111" & -- Manufacturer ID
"1"; -- Required by IEEE Std. 1149.1-1990
attribute REGISTER_ACCESS of TMS320F2812 : entity is
"BOUNDARY (extest, sample), " &
"DEVICE_ID (idcode), " &
"BYPASS (bypass)";
attribute BOUNDARY_LENGTH of TMS320F2812 : entity is 237;
attribute BOUNDARY_REGISTER of TMS320F2812 : entity is
-- num cell port function safe [ccell disval rslt]
"0 ( bc_4, XMPnMC, input, X)," &
"1 ( bc_1, XA(0), output3, X, 2, 1, Z)," &
"2 ( bc_1, *, control, 1)," &
"3 ( bc_4, MDRA, input, X)," &
"4 ( bc_1, MDRA, output3, X, 5, 1, PULL1)," &
"5 ( bc_1, *, control, 1)," &
"6 ( bc_4, XD(0), input, X)," &
"7 ( bc_1, XD(0), output3, X, 8, 1, PULL1)," &
"8 ( bc_1, *, control, 1)," &
"9 ( bc_4, MDXA, input, X)," &
"10 ( bc_1, MDXA, output3, X, 11, 1, Z)," &
"11 ( bc_1, *, control, 1)," &
"12 ( bc_4, XD(1), input, X)," &
"13 ( bc_1, XD(1), output3, X, 8, 1, PULL1)," &
"14 ( bc_4, MCLKRA, input, X)," &
"15 ( bc_1, MCLKRA, output3, X, 16, 1, PULL1)," &
"16 ( bc_1, *, control, 1)," &
"17 ( bc_4, MFSXA, input, X)," &
"18 ( bc_1, MFSXA, output3, X, 19, 1, PULL1)," &
"19 ( bc_1, *, control, 1)," &
"20 ( bc_4, XD(2), input, X)," &
"21 ( bc_1, XD(2), output3, X, 8, 1, PULL1)," &
"22 ( bc_4, MCLKXA, input, X)," &
"23 ( bc_1, MCLKXA, output3, X, 24, 1, PULL1)," &
"24 ( bc_1, *, control, 1)," &
"25 ( bc_4, MFSRA, input, X)," &
"26 ( bc_1, MFSRA, output3, X, 27, 1, PULL1)," &
"27 ( bc_1, *, control, 1)," &
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