📄 sprm180.bsm
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------------------------------------------------------------------------
-- File Type : BSDL Description for Top-Level Entity TMS320F2812 --
------------------------------------------------------------------------
------------------------------------------------------------------------
-- TI TMS320F2812 32-bit 179-pin Fixed-Point DSP with Boundary Scan --
------------------------------------------------------------------------
-- Supported Devices: TMS320F2812 179-pin Rev C and higher --
------------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : TMS320F28x Users Guide --
-- BSDL Revision : 1.2 --
-- Date : 25 Jan 2005
-- BSDL status : TMS --
-- --
-- History: --
--
-- Rev. 1.2, Jan 25, 2005: Made the following changes
-- 1) Renamed ZACS6AND7n to XZCS6AND7n
-- --
-- Rev. 1.1, Jan 14, 2005: Made the following changes (DMA) --
-- --
-- 1) Changed the following pin names throughout the document to --
-- be consistent with the device datasheet, SPRS174. --
-- --
-- OLD NAME NEW NAME --
-- -------- -------- --
-- VDDAFL VDDAIO --
-- VDDSFL VDDIO --
-- VSSA3 VSSAIO --
-- ADCIN0 ADCINA --
-- ADCIN1 ADCINB --
-- C1TRIPN C1TRIPn --
-- C2TRIPN C2TRIPn --
-- C3TRIPN C3TRIPn --
-- C4TRIPN C4TRIPn --
-- C5TRIPN C5TRIPn --
-- C6TRIPN C6TRIPn --
-- T1CTRIP_PDPINTAn T1CTRIPn_PDPINTAn --
-- T2CTRIP_EVASOCn T2CTRIPn_EVASOCn --
-- T3CTRIP_PDPINTBn T3CTRIPn_PDPINTBn --
-- T4CTRIP_EVBSOCn T4CTRIPn_EVBSOCn --
-- XINT1_XBION XINT1_XBIOn --
-- x1 x1_xclkin --
-- xa XA --
-- xclkout XCLKOUT --
-- xd XD --
-- xholdan XHOLDAn --
-- xholdn XHOLDn --
-- xmpnmc XMPnMC --
-- xrdn XRDn --
-- xready XREADY --
-- xrnw XRnW --
-- xrsn XRSn --
-- xwen XWEn --
-- xzcs0and1n XZCS0AND1n --
-- xzcs2n XZCS2n --
-- xzcs6and7n XZCS6AND7n --
-- --
-- 2) Adjusted order of PHYSICAL_PIN_STRING entries to match --
-- the order of the PHYSICAL_PIN_MAP entries. --
-- --
-- 3) Corrected the "Device Pins not testable ..." comment in --
-- this header. --
-- from: X2/XCLKIN, X1 --
-- to: X1/XCLKIN, X2 --
-- --
-- 4) Added missing balls C10 and K1 to Vss PIN_MAP_STRING. --
-- --
-- Rev. 1.0, Oct 15, 2003: Original --
-- --
------------------------------------------------------------------------
--
-- Initialization Requirements for Boundary Scan Test
-- --------------------------------------------------
--
-- The F281x DSPs use the JTAG port for boundary scan tests, emulation
-- capability and factory test purposes. To use boundary scan test,
-- the following pin configuration must be used:
--
-- TESTSEL = 0
-- EMU1 = 0
-- EMU0 = 1
-- TRSTN = 0 -> 1 ( transitioning to a 1 will latch the device into
-- boundary scan mode )
--
-- TRSTN is a reset to the JTAG state machine (active low), hence it has
-- to be pulled high before any JTAG scans are made.
--
-- F281x Devices have two taps - one for the CPU and one for boundary scan.
-- The boundary scan IR size is 3 bits.
--
-- Device Pins not testable by Boundary Scan
-- ------------------------------------------
-- The following pins cannot be tested through boundary scan:
-- EMU0, EMU1, X1/XCLKIN, X2, TESTSEL, TEST1, TEST2, and all the analog pins
--
--
-- IMPORTANT NOTICE
-- Texas Instruments Incorporated (TI) reserves the right to make
-- changes to its products or to discontinue any semiconductor
-- product or service without notice, and advises its customers to
-- obtain the latest version of the relevant information to
-- verify, before placing orders, that the information being
-- relied on is current.
-- TI warrants performance of its semiconductor products and
-- related software to the specifications applicable at the time
-- of sale in accordance with TI's standard warranty. Testing and
-- other quality control techniques are utilized to the extent TI
-- deems necessary to support this warranty. Specific testing of
-- all parameters of each device is not necessarily performed,
-- except those mandated by government requirements.
--
-- Certain applications using semiconductor devices may involve
-- potential risks of death, personal injury, or severe property
-- or environmental damage ("Critical Applications").
--
-- TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
-- AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
-- LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
-- CRITICAL APPLICATIONS.
--
-- Inclusion of TI products in such applications is understood
-- to be fully at the risk of the customer. Use of TI products
-- in such applications requires the written approval of an
-- appropriate TI officer. Questions concerning potential risk
-- applications should be directed to TI through a local SC sales
-- office.
-- In order to minimize risks associated with the customer's
-- applications, adequate design and operating safeguards should
-- be provided by the
-- customer to minimize inherent or procedural hazards.
--
-- TI assumes no liability for applications assistance, customer
-- product design, software performance, or infringement of
-- patents or services described herein. Nor does TI warrant or
-- represent that any license, either express or implied, is
-- granted under any patent right, copyright, mask work right, or
-- other intellectual property right of TI covering or relating
-- to any combination, machine, or process in which such
-- semiconductor products or services might be or are used.
-- Copyright (c) 2000, Texas Instruments Incorporated
------------------------------------------------------------------------
entity TMS320F2812 is
generic(PHYSICAL_PIN_MAP : string := "GHH");
port (
VDDAIO : linkage bit;
VDDA1 : linkage bit;
VSSA1 : linkage bit;
VDD : linkage bit_vector(9 downto 0);
VSS : linkage bit_vector(15 downto 0);
VDDIO : linkage bit_vector(5 downto 0);
VDD3VFL : linkage bit;
VDD1 : linkage bit;
VSS1 : linkage bit;
VDDA2 : linkage bit;
VSSA2 : linkage bit;
VSSAIO : linkage bit;
ADCINA : linkage bit_vector(7 downto 0);
ADCINB : linkage bit_vector(7 downto 0);
ADCLO : linkage bit;
ADCREFM : linkage bit;
ADCREFP : linkage bit;
ADCRESEXT : linkage bit;
AVSSREFBG : linkage bit;
AVDDREFBG : linkage bit;
ADCBGREFIN : linkage bit;
C3TRIPn : inout bit;
C2TRIPn : inout bit;
C1TRIPn : inout bit;
TCLKINA : inout bit;
TDIRA : inout bit;
CAP3_QEPI1 : inout bit;
CAP2_QEP2 : inout bit;
CAP1_QEP1 : inout bit;
T2PWM_T2CMP : inout bit;
T1PWM_T1CMP : inout bit;
PWM6 : inout bit;
PWM5 : inout bit;
PWM4 : inout bit;
PWM3 : inout bit;
PWM2 : inout bit;
PWM1 : inout bit;
C6TRIPn : inout bit;
C5TRIPn : inout bit;
C4TRIPn : inout bit;
TCLKINB : inout bit;
TDIRB : inout bit;
CAP6_QEPI2 : inout bit;
CAP5_QEP4 : inout bit;
CAP4_QEP3 : inout bit;
T4PWM_T4CMP : inout bit;
T3PWM_T3CMP : inout bit;
PWM12 : inout bit;
PWM11 : inout bit;
PWM10 : inout bit;
PWM9 : inout bit;
PWM8 : inout bit;
PWM7 : inout bit;
T1CTRIPn_PDPINTAn : inout bit;
T2CTRIPn_EVASOCn : inout bit;
T3CTRIPn_PDPINTBn : inout bit;
T4CTRIPn_EVBSOCn : inout bit;
XINT1_XBIOn : inout bit;
XINT2_ADCSOC : inout bit;
XNMI_XINT13 : inout bit;
XF_XPLLDISn : inout bit;
MDRA : inout bit;
MDXA : inout bit;
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