📄 l4.h
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#define MIB_RX_AEP1 0x353
#define MIB_RX_IPEP0 0x354
#define MIB_RX_IPEP1 0x355
#define MIB_RX_ICMPEP0 0x356
#define MIB_RX_ICMPEP1 0x357
#define MIB_RX_IGMPEP0 0x358
#define MIB_RX_IGMPEP1 0x359
#define MIB_RX_TCPEP0 0x35A
#define MIB_RX_TCPEP1 0x35B
#define MIB_RX_UDPEP0 0x35C
#define MIB_RX_UDPEP1 0x35D
#define MIB_RX_DISIP0 0x35E
#define MIB_RX_DISIP1 0x35F
#define MIB_RX_DISPPP0 0x360
#define MIB_RX_DISPPP1 0x361
#define MIB_TX_O0 0x364 /* TX */
#define MIB_TX_O1 0x365
#define MIB_TX_O2 0x366
#define MIB_TX_UP0 0x368
#define MIB_TX_UP1 0x369
#define MIB_TX_NUP0 0x36A
#define MIB_TX_NUP1 0x36B
#define MIB_ARP_RXPKT 0x36C
#define MIB_ICMP_RXPKT 0x36D
#define MIB_IGMP_RXPKT 0x36E
#define MIB_PPPOE_RXPKT 0x36F
#define MIB_S0_RXPKT 0x370
#define MIB_S1_RXPKT 0x371
#define MIB_S2_RXPKT 0x372
#define MIB_S3_RXPKT 0x373
#define MIB_ARP_TXPKT 0x374
#define MIB_ICMP_TXPKT 0x375
#define MIB_IGMP_TXPKT 0x376
#define MIB_PPPOE_TXPKT 0x377
#define MIB_S0_TXPKT 0x378
#define MIB_S1_TXPKT 0x379
#define MIB_S2_TXPKT 0x37A
#define MIB_S3_TXPKT 0x37B
#define MIB_STAT3 0x37C
#define MIB_STAT4 0x37D
/* Bit Defination for Registers */
/* System Control */
/* System Control 0 */
#define PME 0x80
#define FAST_SIM 0x40
#define CON_TYPE 0x20
#define PLL_RST 0x04
#define DMA_RST 0x02
#define SW_RST 0x01
/* System Control 1 */
//#define ARP_RST 0x80 //Cancel it in Spec V0.54
#define ICMP_RST 0x40
#define IGMP_RST 0x20
#define S0_RST 0x10
#define S1_RST 0x08
#define S2_RST 0x04
#define S3_RST 0x02
#define PPPOE_RST 0x01
/* System Control 2 */
/* External Data Memory Bus Wait State */
#if 0
#define BUS_RDMIN_MASK 0x38
#define BUS_RDMIN_SHIFT 0x03
#define BUS_WRMIN_MASK 0x07
#define BUS_WRMIN_SHIFT 0x00
#else
#define IPROGRAM_ENABLE 0x80
#define IPROGRAM_DISABLE 0x00
#define IPROGRAM_BOTTOM1K 0x40
#define IPROGRAM_TOP1K 0x80
#endif
/* Global Interrupt Enable */
#define SYS_INTEN 0x80
#define MAC_INTEN 0x40
#define ICMP_INTEN 0x20
#define S0_INTEN 0x10
#define S1_INTEN 0x08
#define S2_INTEN 0x04
#define S3_INTEN 0x02
#define PPPOE_INTEN 0x01
/* Global Interrupt Status */
#define SYS_INT 0x80
#define MAC_INT 0x40
#define ICMP_INT 0x20
#define S0_INT 0x10
#define S1_INT 0x08
#define S2_INT 0x04
#define S3_INT 0x02
#define PPPOE_INT 0x01
/* Global Interrupt Priority */
#define SYS_INTPR 0x80
#define MAC_INTPR 0x40
#define ICMP_INTPR 0x20
#define S0_INTPR 0x10
#define S1_INTPR 0x08
#define S2_INTPR 0x04
#define S3_INTPR 0x02
#define PPPOE_INTPR 0x01
/* Global Interrupt Generation (For driver use only) */
#define SYS_INTG 0x80
#define MAC_INTG 0x40
#define ICMP_INTG 0x20
#define S0_INTG 0x10
#define S1_INTG 0x08
#define S2_INTG 0x04
#define S3_INTG 0x02
#define PPPOE_INTG 0x01
/* System Interrupt Enable */
#define EXT_INTE 0x80
#define ARP_HNEE 0x40
#define RARP_TOE 0x20
#define RARP_IPAAE 0x10
#define IP_CFTE 0x08
#define GATE_TOE 0x04
#define MIB_COE 0x02
#define RX_WUEE 0x01
/* MAC Interrupt Enable */
#define DMA_CMPE 0x80
#define MAC_RFEE 0x40
#define MAC_LKE 0x20
#define MAC_TFCEE 0x10
#define MAC_RFOE 0x08
#define MAC_TFEE 0x04
#define MAC_RCE 0x02
#define MAC_TCE 0x01
/* ICMP/IGMP Interrupt Enable */
#define ICMP_RXPUE 0x80
#define IGMP_LGE 0x40
#define IGMP_JGE 0x20
#define ICMP_TFCEE 0x10
#define ICMP_RFOE 0x08
#define ICMP_TFEE 0x04
#define ICMP_RCE 0x02
#define ICMP_TCE 0x01
/* Socket n Interrupt Enable */
#define SOCK_RXFPE 0x80
#define SOCK_SME 0x40
#define SOCK_RTOE 0x20
#define SOCK_TFCEE 0x10
#define SOCK_RFOE 0x08
#define SOCK_TFEE 0x04
#define SOCK_RCE 0x02
#define SOCK_TCE 0x01
/* PPPoE Interrupt Enable */
#define PPPOE_AUFAEN 0x80
#define PPPOE_AUOKEN 0x40
#define PPPOE_TOEN 0x20
#define PPPOE_TFCEEN 0x10
#define PPPOE_RFOEN 0x08
#define PPPOE_TFEEN 0x04
#define PPPOE_RCEN 0x02
#define PPPOE_TCEN 0x01
/* System Interrupt Status */
#define EXT_INT 0x80
#define ARP_HNE 0x40
#define RARP_TO 0x20
#define RARP_IPAA 0x10
#define IP_CFT 0x08
#define GATE_TO 0x04
#define MIB_CO 0x02
#define RX_WUE 0x01
/* MAC Interrupt Status */
#define DMA_CMP 0x80
#define MAC_RFE 0x40
#define MAC_LK 0x20
#define MAC_TFCE 0x10
#define MAC_RFO 0x08
#define MAC_TFE 0x04
#define MAC_RC 0x02
#define MAC_TC 0x01
/* ICMP/IGMP Interrupt Status */
#define ICMP_RXPU 0x80
#define IGMP_LG 0x40
#define IGMP_JG 0x20
#define ICMP_TFCE 0x10
#define ICMP_RFO 0x08
#define ICMP_TFE 0x04
#define ICMP_RC 0x02
#define ICMP_TC 0x01
/* Socket n Interrupt Status */
#define SOCK_RXFP 0x80
#define SOCK_SM 0x40
#define SOCK_RTO 0x20
#define SOCK_TFCE 0x10
#define SOCK_RFO 0x08
#define SOCK_TFE 0x04
#define SOCK_RC 0x02
#define SOCK_TC 0x01
/* PPPoE Interrupt Status */
#define PPPOE_AUFA 0x80
#define PPPOE_AUOK 0x40
#define PPPOE_TO 0x20
#define PPPOE_TFCE 0x10
#define PPPOE_RFO 0x08
#define PPPOE_TFE 0x04
#define PPPOE_RC 0x02
#define PPPOE_TC 0x01
/* DMA control */
#define DMA_ST 0x80
/* CSB control */
#define CSB0_EN 0x01
#define CSB1_EN 0x02
#define CSB2_EN 0x04
#define CSB3_EN 0x08
#define CSB0_HADD 0x10
#define CSB1_HADD 0x20
#define CSB2_HADD 0x40
#define CSB3_HADD 0x80
#define CSB0_WS_MASK 0x0F
#define CSB1_WS_MASK 0xF0
#define CSB2_WS_MASK 0x0F
#define CSB3_WS_MASK 0xF0
/* MAC Layer */
/* MAC TX Descriptor Control/Status(Hardware Debug) */
#define MAC_TDSC_SRC 0x80
#define CRSL 0x10
#define LC 0x08
#define DEFER 0x04
#define MAC_TXABT 0x02
#define MAC_TXOK 0x01
/* MII Management Control 0 */
#define PHY_RST 0x80
#define MDIO_RD 0x40
#define MDIO_WR 0x20
#define PHY_ADD_MASK 0x1f
#define PHY_ADD_SHIFT 0x00
/* MII Management Control 1 */
#define REG_ADD_MASK 0x1f
#define REG_ADD_SHIFT 0x00
/* Network MAC Configuration 0 */
#define MAC_RXON 0x80
#define MAC_TXON 0x40
#define LBM_MASK 0x30
#define LBM_NORMAL 0x00
#define LBM_MAC 0x10
#define LBM_PHY 0x20
#define PAUSE 0x08
#define NLNK 0x04
#define NSPD 0x02
#define NDPX 0x01
/* Network MAC Configuration 1 */
#define PHY_APE 0x80
#define AEP 0x40
#define ALP 0x20
#define ARP 0x10
#define ABP 0x08
#define AMP 0x04
#define ADP 0x02
#define AAUP 0x01
/* Wake-Up Control/Status */
#define RXMPS 0x20
#define LSCS 0x10
#define MPE 0x02
#define LSCE 0x01
/* Flow Control */
#define FCE 0x80
#define RPF 0x40
#define MAC_PS 0x20
#define TPF 0x10
#define MAC_RXAHT 0x02
#define MAC_RXALT 0x01
/* VLAN Tag Control */
#define QTR 0x08
#define DUF 0x04
#define DTF 0x02
#define QTAG_EN 0x01
/* VLAN ID 1 */
#define VUP_MASK 0xE0
#define VUP_SHIFT 0x05
#define VID_H_MASK 0x0F
#define VID_H_SHIFT 0x0F
/* ARP/RARP Layer */
/* ARP Control/Status */
#define SGARP 0x80
#define GARP_PC_MASK 0x70
#define GARP_PC_SHIFT 0x04
#define ARP_ETHERPKT 0x04
#define ARP_ENC_MASK 0x06
#define ARP_QTAG_EN 0x02
#define CLR_ARP 0x01
/* ARP Timer */
#define ARP_TM_MASK 0xc0
#define ARP_TM_10MIN 0x00
#define ARP_TM_15MIN 0x40
#define ARP_TM_20MIN 0x80
#define ARP_TM_25MIN 0xC0
//#define ARP_PC_MASK 0x30
//#define ARP_PC_1 0x10
//#define ARP_PC_2 0x20
//#define ARP_PC_3 0x30
//#define ARP_PP_MASK 0x0c
//#define ARP_PP_1S 0x00
//#define ARP_PP_2S 0x04
//#define ARP_PP_3S 0x08
//#define ARP_PP_4S 0x0c
#define ARP_TV_MASK 0x03
#define ARP_TV_300MS 0x00
#define ARP_TV_600MS 0x01
#define ARP_TV_900MS 0x02
/* ARP Host Non-exist Channel */
#define ICMP_HNE 0x10
#define S3_HNE 0x08
#define S2_HNE 0x04
#define S1_HNE 0x02
#define S0_HNE 0x01
/* RARP Control/Timer */
#define RARP_TO_MASK 0xf0
#define RARP_TO_SHIFT 0x04
#define RARP_EN 0x01
/* IP Layer */
/* Checksum Control */
#define UDP_CGE 0x04
#define IP_CGE 0x02
#define CVE 0x01
/* Default Gateway Control */
#define GW_TE 0x80
#define GW_TO_MASK 0x60
#define GW_TO_10MIN 0x00
#define GW_TO_20MIN 0x20
#define GW_TO_30MIN 0x40
#define GW_TO_40MIN 0x60
/* ICMP Layer */
/* ICMP TX Descriptor Control/Status */
#define ICMP_TDSC_RC 0x80
#define ICMP_TXOK 0x01
/* ICMP Channel Control */
#define ICMP_CE 0x80
#define ICMP_TXEN 0x40
#define ICMP_RXEN 0x20
#define ICMP_RF_DISE 0x10
#define ICMP_TF_ABT 0x08
#define ICMP_AU_UBP 0x01
/* IGMP Layer */
/* IGMP Channel Control */
#define IGMP_EN 0x80
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