jiaotongdeng.txt

EDA常用计数函数VHDL程序设计,基于VHDL的交通灯设计实例&分频器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity traffic is
port(clk,urgency:in std_logic;
east_west:buffer std_logic_vector(7 downto 0);
south_north:buffer std_logic_vector(7 downto 0);
led:buffer std_logic_vector(5 downto 0));
end traffic;
architecture arch of traffic is
begin
process(clk,urgency)
begin
if urgency='1' then
led<="100001";
elsif(clk'event and clk='1') then
if(east_west=6 and south_north=1) then
east_west<="00000101"; 
south_north<="00000101";
led<="100010";
elsif(east_west=1 and south_north=1 and led(5)='1') then
east_west<="01000000";
south_north<="01000101";
led<="001001";
elsif(east_west=1 and south_north=6) then
east_west<="00000101";
south_north<="00000101";
led<="010001";
elsif((east_west=1 and south_north=1 and led(0)='1')or east_west=0) then
east_west<="01000101";
south_north<="01000000";
led<="100100";
elsif(east_west(3 downto 0)="0000") then
east_west<=east_west-7;
south_north<=south_north-1;
elsif(south_north(3 downto 0)="0000") then
east_west<=east_west-1;
south_north<=south_north-7;
else
east_west<=east_west-1;
south_north<=south_north-1;
end if;
end if;
end process;
end arch;