fenpin.txt

EDA常用计数函数VHDL程序设计,基于VHDL的交通灯设计实例&分频器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity frequence_div is
port(data:in std_logic_vector(15 downto 0);
clk:in std_logic;
clkout:out std_logic);
end entity frequence_div;
architecture bh of frequence_div is
signal reg_data:integer range 0 to 65536;
signal d:integer range 0 to 65536:=0;
signal fo:std_logic;
begin
reg_data<=conv_integer(data);
process(clk)
begin
if(clk'event and clk='1')then
if d=(reg_data-1)then
d<=0;
fo<=not fo;
else
d<=d+1;
clkout<=fo;
end if;
end if;
end process;
end architecture bh;