howto_sse2.lyx

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\layout Standard

Copies words from the high quadword of the source operand (second operand)
 and inserts them in the high quadword of the destination operand (first
 operand) at word locations selected with the order operand (third operand).
 For the PSHUFHW instruction, each 2-bit field in the order operand selects
 the contents of one word location in the high quadword of the destination
 operand.
 The binary encodings of the order operand fields select words (0, 1, 2,
 or 3 4) from the high quadword of the source operand to be copied to the
 destination operand.
 The low quadword of the source operand is copied to the low quadword of
 the destination operand.
\layout Itemize

PSHUFLW xmm1, xmm2/m128, imm8 
\layout Standard

Source: an XMM register or a 128-bit memory location.
 
\layout Standard

Destination: an XMM register.
 
\layout Standard

Order: an 8-bit immediate.
\layout Standard

Latency: 2 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Copies words from the low quadword of the source operand (second operand)
 and inserts them in the low quadword of the destination operand (first
 operand) at word locations selected with the order operand (third operand).
 For the PSHUFLW instruction, each 2-bit field in the order operand selects
 the contents of one word location in the low quadword of the destination
 operand.
 The binary encodings of the order operand fields select words (0, 1, 2,
 or 3) from the low quadword of the source operand to be copied to the destinati
on operand.
 The high quadword of the source operand is copied to the high quadword
 of the destination operand.
\layout Standard

Note that this instruction permits a word in the low quadword of the source
 operand to be copied to more than one word location in the low quadword
 of the destination operand.
\layout Standard


\begin_inset Graphics
	filename images_sse2/NewPSHUFLW.gif
	lyxscale 55
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PSHUFD xmm1, xmm2/m128, imm8 
\layout Standard

Source: an XMM register or a 128-bit memory location.
 
\layout Standard

Destination: an XMM register.
 
\layout Standard

Order: an 8-bit immediate.
\layout Standard

Latency: 4 Throughput: 2
\layout Standard

Purpose: Copies doublewords from source operand (second operand) and inserts
 them in the destination operand (first operand) at locations selected with
 the order operand (third operand).
 Each 2-bit field in the order operand selects the contents of one doubleword
 location in the destination operand.
 For example, bits 0 and 1 of the order operand selects the contents of
 doubleword 0 of the destination operand.
 The encoding of bits 0 and 1 of the order operand determines which doubleword
 from the source operand will be copied to doubleword 0 of the destination
 operand.
\layout Standard


\begin_inset Graphics
	filename images_sse2/NewPSHUFD.gif
	lyxscale 55
	scale 55
	keepAspectRatio

\end_inset 


\layout Subsection

Logical Instructions
\layout Standard

MMX-
\layout Standard

Usage: instruction destination, source 
\layout Standard

Destination: MMX register.
 
\layout Standard

Source: MMX register or 64-bit memory operand.
\layout Itemize

PAND Bitwise AND
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PAND performs a bitwise logical AND on 64 bits of the source and destination
 operands, and returns the result to destination.
 Each bit of the result of the PAND instruction is set to 1 if the corresponding
 bits of the operands are 1.
 Otherwise, it is set to 0.
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPAND.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PANDN Bitwise AND NOT
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PANDN performs a bitwise logical NOT on the 64 bits of the destination operand.
 The NOT inverts each of the 64 bits of the destination register so that
 every 1 becomes a 0, and visa versa.
 The instruction then performs a bitwise logical AND on the inverted 64
 bits of the destination operand and on the source operand.
 Each bit of the result of the AND instruction is set to 1 if the corresponding
 bits are 1.
 Otherwise, it is set to 0.
 The result is written to the destination register.
 
\layout Itemize

POR Bitwise OR
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

POR performs a bitwise logical OR on 64 bits of the destination and source
 operands, and writes the result to the destination register.
 Each bit of the result is set to 0 if the corresponding bits of the two
 operands are 0.
 Otherwise, the bit is 1.
\layout Itemize

PXOR Bitwise XOR
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

The PXOR instruction performs a bitwise logical XOR on the 64 bits of the
 destination with the source operands and writes the result to destination
 register.
 Each bit of the result is 1 if the corresponding bits of the two operands
 are different.
 Each bit is 0 if the corresponding bits of the operands are the same.
\layout Standard

SSE-
\layout Itemize

ANDNPS xmm1,xmm2/mem128 
\layout Standard

Latency : 4 Throughput : 2
\layout Standard

Purpose:
\layout Standard

ANDNPS inverts the bits of the four single-precision floating-point values
 in the destination register, and then performs a logical AND between the
 four single-precision floating-point values in the source operand and the
 temporary inverted result, storing the result in the destination register.
\layout Standard

The destination is an XMM register.
 The source operand can be either an XMM register or a 128-bit memory location.
 B.5.4 ANDPS: Bitwise Logical AND For Single FP
\layout Itemize

ANDPS xmm1,xmm2/mem128 
\layout Standard

Latency : 4 Throughput : 2
\layout Standard

Purpose:
\layout Standard

ANDPS performs a bitwise logical AND of the four single-precision floating
 point values in the source and destination operand, and stores the result
 in the destination register.
\layout Standard

The destination is an XMM register.
 The source operand can be either an XMM register or a 128-bit memory location.
 
\layout Itemize

ORPS xmm1,xmm2/m128 
\layout Standard

Latency : 4 Throughput : 2
\layout Standard

Purpose:
\layout Standard

ORPS return a bit-wise logical OR between xmm1 and xmm2/mem, and stores
 the result in xmm1.
 If the source operand is a memory location, it must be aligned to a 16-byte
 boundary
\layout Itemize

XORPS xmm1,xmm2/m128
\layout Standard

Latency : 4 Throughput : 2
\layout Standard

Purpose:
\layout Standard

XORPS returns a bit-wise logical XOR between the source and destination
 operands, storing the result in the destination operand.
 
\layout Standard

SSE2-
\layout Itemize

ANDPD xmm, xmm 
\layout Standard

Latency: 4 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Parallel and operation on all 128 bits
\layout Itemize

ANDNPD xmm, xmm 
\layout Standard

Latency: 4 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Parallel and not operation on all 128 bits
\layout Itemize

ORPD xmm, xmm 
\layout Standard

Latency: 4 Throughput: 2
\layout Standard

Purpose:
\layout Itemize

XORPD xmm, xmm 
\layout Standard

Latency: 4 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Parallel xor operation on all 128 bits
\layout Subsection

Shift Instructions
\layout Standard

MMX-
\layout Standard

Usage: instruction destination, source 
\layout Standard

Destination: MMX register.
 
\layout Standard

Source(count operand): Either MMX register, a 64-bit memory operand, or
 an immediate 8-bit operand.
\layout Itemize

PSLLD Packed Shift Left Logical, Doubleword
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSLLD shifts the bits of the first operand to the left by the amount of
 bits specified in the count operand and returns the result to the destination
 register.
 The empty low-order bits are cleared (set to zero).
 If the value specified by the count operand is greater than 31 (1Fh) the
 destination is set to all zeros.
\layout Itemize

PSLLQ Packed Shift Left Logical, Quadword
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSLLQ shifts the bits of the first operand to the left by the amount of
 bits specified in the count operand and returns the result to the destination
 register.
 The empty low-order bits are cleared (set to zero).
 If the value specified by the second operand is greater than 63 (3Fh) the
 destination is set to all zeros.
\layout Itemize

PSLLW Packed Shift Left Logical, Word
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSLLW shifts the bits of the first operand to the left by the amount of
 bits specified in the count operand and returns the result to the destination
 register.
 The empty low-order bits are cleared (set to zero).
 If the value specified by the second operand is greater than 15 (0Fh) the
 destination is set to all zeros.
 
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPSLL.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PSRLD Packed Shift Right Logical, Doubleword
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSRLD performs a shift-logical-right operation on each of the two doublewords
 in the destination operand.
 The count operand determines how many bits to right-shift.
 The new high-order bits are cleared (set to zero).
 If the value specified by the count operand is greater than 31 (1Fh) the
 destination is set to all zeros.
\layout Itemize

PSRLQ Packed Shift Right Logical, Quadword
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSRLQ performs a shift-logical-right operation on the quardword destination
 operand.
 The count operand determines how many bits to right-shift.
 The new high-order bits are cleared (set to zero).
 If the value specified by the count operand is greater than 63 (3Fh) the
 destination is set to all zeros.
\layout Itemize

PSRLW Packed Shift Right Logical, Word
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSRLW performs a shift-logical-right operation on each of the four words
 in the destination operand.
 The count operand determines how many bits to right-shift.
 The new high-order bits are cleared (set to zero).
 If the value specified by the count operand is greater than 15 (0Fh) the
 destination is set to all zeros.
 
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPSRL.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PSRAD Packed Shift Right Arithmetic, Doubleword
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSRAD performs a shift-arithmetic-right (SAR) operation on each of the two
 doublewords in the destination operand.
 The count operand determines the number of bits to right-shift.
 The new high-order bits of each doubleword are filled with the initial
 value of the sign bit of the doubleword.
 If the value specified by count is greater than 31 (1Fh), each doubleword
 is filled with the initial value of its sign bit.
\layout Itemize

PSRAW Packed Shift Right Arithmetic, Word
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSRAW performs a shift-arithmetic-right (SAR) operation on each of the four
 words in the destination operand.
 The count operand determines the number of bits to right-shift.
 The new high-order bits of each word are filled with the initial value
 of the sign bit of the word.
 If the value specified by count is greater than 15 (0Fh), each word is
 filled with the initial value of its sign bit.
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPSRA.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Standard

SSE2-
\layout Itemize

PSLLDQ xmm1, imm8 
\layout Standard

Destination: an XMM register.
\layout Standard

Count: an 8-bit immediate.
\layout Standard

Latency: 4 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Shifts the destination operand (first operand) to the left by the number
 of bytes specified in the count operand (second operand).
 The empty low-order bytes are cleared (set to all 0s).
 If the value specified by the count operand is greater than 15, the destination
 operand is set to all 0s.
 
\layout Standard


\begin_inset Graphics
	filename images_sse2/NewPSLLDQ.gif
	lyxscale 55
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PSRLDQ xmm1, imm8 
\layout Standard

Destination: an XMM register.
\layout Standard

Count: an 8-bit immediate.
\layout Standard

Latency: 4 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Shifts the destination operand (first operand) to the right by the number
 of bytes specified in the count operand (second operand).
 The empty