howto_sse2.lyx

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 doublewords from the destination operand into four signed words in the
 destination register.
 If the signed value of a doubleword is larger or smaller than the range
 of a signed word, the value is saturated (in the case of an overflow to
 7FFFh, and in the case of an underflow to 8000h).
\layout Itemize

PACKSSWB Pack Words into Bytes (Signed with Saturation)
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PACKSSWB packs four signed words from the source operand and four signed
 words from the destination operand into eight signed bytes in the destination
 register.
 If the signed value of a word is larger or smaller than the range of a
 signed byte, the value is saturated (in the case of an overflow to 7Fh,
 and in the case of an underflow to 80h).
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPACKSS.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PACKUSWB Pack Words into Bytes (Unsigned with Saturation)
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PACKUSWB packs and saturates four signed words of the source operand and
 four signed words of the destination operand into eight unsigned bytes.
 The result is written to the destination operand.
 If the signed value of a word is larger or smaller than the range of an
 unsigned byte, the value is saturated (in the case of an overflow to 0FFh,
 and in the case of an underflow to 00h).
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPACKUS.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PUNPCKHBW Unpack (interleave) High-order Bytes
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PUNPCKHBW interleaves the four high-order bytes of the source operand and
 the four high-order bytes of the destination operand and writes them to
 the destination.
 When unpacking from a memory operand, the full 64-bit operand is accessed
 from memory.
 PUNPCKHBW uses only the high-order 32 bits.
\layout Standard

Note If the source operand is all zeros, this instruction converts bytes
 to unsigned words.
\layout Itemize

PUNPCKHDQ Unpack (interleave) High-order Doublewords
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PUNPCKHDQ interleaves the high-order doubleword of the source operand and
 the high-order doubleword of the destination operand and writes them to
 the destination.
 When unpacking from a memory operand, the full 64-bit operand is accessed
 from memory.
 PUNPCKHDQ uses only the high-order 32 bits.
\layout Itemize

PUNPCKHWD Unpack (interleave) High-order Words
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PUNPCKHWD interleaves the two high-order words of the source operand and
 the two high-order words of the destination operand and writes them to
 the destination.
 When unpacking from a memory operand, the full 64-bit operand is accessed
 from memory.
 PUNPCKHWD uses only the high-order 32 bits.
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPUNPCKH.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PUNPCKLBW Unpack (interleave) Low-order Bytes
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PUNPCKLBW interleaves the four low-order bytes of the source operand and
 the four low-order bytes of the destination operand and writes them to
 the destination.
 When unpacking from a memory operand, only 32 bits are accessed.
\layout Itemize

PUNPCKLDQ Unpack (interleave) Low-order Doublewords
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PUNPCKLDQ interleaves the low-order doubleword of the source operand and
 the low-order doubleword of the destination operand and writes them to
 the destination.
 When unpacking from a memory operand, only 32 bits are accessed.
\layout Itemize

PUNPCKLWD Unpack (interleave) Low-order Words
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PUNPCKLWD interleaves the two low-order words of the source operand and
 the two low-order words of the destination operand and writes them to the
 destination.
 When unpacking from a memory operand, only 32 bits are accessed.
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPUNPCKL.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Standard

SSE-
\layout Itemize

CVTPS2PI mm,xmm/mem64 
\layout Standard

Latency : 7 Throughput : 2
\layout Standard

Purpose:
\layout Standard

CVTPS2PI converts two packed single-precision FP values from the source
 operand to two packed signed doublewords in the destination operand.
\layout Standard

The destination operand is an MMX register.
 The source can be either an XMM register or a 64-bit memory location.
 If the source is a register, the input values are in the low quadword.
\layout Itemize

CVTSD2SS xmm1,xmm2/mem64 
\layout Standard

Purpose:
\layout Standard

CVTSD2SS converts a double-precision FP value from the source perand to
 a single-precision FP value in the low doubleword of the estination operand.
 The upper 3 doublewords are left unchanged.
\layout Standard

The destination operand is an XMM register.
 The source can be either an XMM register or a 64-bit memory location.
 If the source is a register, the input value is in the low quadword.
\layout Itemize

CVTSI2SS xmm,r/m32 
\layout Standard

Latency : 11 Throughput : 2
\layout Standard

Purpose:
\layout Standard

CVTSI2SS converts a signed doubleword from the source operand to a single-precis
ion FP value in the low doubleword of the destination operand.
 The upper 3 doublewords are left unchanged.
\layout Standard

The destination operand is an XMM register.
 The source can be either a general purpose register or a 32-bit memory
 location.
\layout Itemize

CVTSS2SI reg32,xmm/mem32 
\layout Standard

Latency : 8 Throughput : 2
\layout Standard

Purpose:
\layout Standard

CVTSS2SI converts a single-precision FP value from the source operand to
 a signed doubleword in the destination operand.
\layout Standard

The destination operand is a general purpose register.
 The source can be either an XMM register or a 32-bit memory location.
 If the source is a register, the input value is in the low doubleword.
\layout Itemize

CVTTPS2PI mm,xmm/mem64 
\layout Standard

Latency : 7 Throughput : 2
\layout Standard

Purpose:
\layout Standard

CVTTPS2PI converts two packed single-precision FP values in the source operand
 to two packed signed doublewords in the destination operand.
 If the result is inexact, it is truncated (rounded toward zero).
 If the source is a register, the input values are in the low quadword.
\layout Standard

The destination operand is an MMX register.
 The source can be either an XMM register or a 64-bit memory location.
 If the source is a register, the input value is in the low quadword.
\layout Itemize

CVTTSS2SI reg32,xmm/mem32
\layout Standard

Latency : 8 Throughput : 2
\layout Standard

Purpose:
\layout Standard

CVTTSS2SI converts a single-precision FP value in the source operand to
 a signed doubleword in the destination operand.
 If the result is inexact, it is truncated (rounded toward zero).
\layout Standard

The destination operand is a general purpose register.
 The source can be either an XMM register or a 32-bit memory location.
 If the source is a register, the input value is in the low doubleword.
\layout Itemize

UNPCKHPS xmm1,xmm2/m128 
\layout Standard

Latency : 6 Throughput : 2
\layout Standard

Purpose:
\layout Standard

UNPCKHPS performs an interleaved unpack of the high-order data elements
 of the source and destination operands, saving the result in xmm1.
 It ignores the lower half of the sources.
\layout Standard

The operation of this instruction is:
\layout Standard

dst[31-0] = dst[95-64]
\layout Standard

dst[63-32] = src[95-64]
\layout Standard

dst[95-64] = dst[127-96]
\layout Standard

dst[127-96] = src[127-96]
\layout Itemize

UNPCKLPS xmm1,xmm2/m128 
\layout Standard

Latency : 4 Throughput : 2
\layout Standard

Purpose:
\layout Standard

UNPCKLPS performs an interleaved unpack of the low-order data elements of
 the source and destination operands, saving the result in xmm1.
 It ignores the lower half of the sources.
\layout Standard

The operation of this instruction is:
\layout Standard

dst[31-0] = dst[31-0]
\layout Standard

dst[63-32] = src[31-0]
\layout Standard

dst[95-64] = dst[63-32]
\layout Standard

dst[127-96] = src[63-32]
\layout Itemize

SHUFPS xmm1,xmm2/m128,imm8 
\layout Standard

Latency : 6 Throughput : 2
\layout Standard

Purpose:
\layout Standard

SHUFPS moves two of the packed single-precision FP values from the destination
 operand into the low quadword of the destination operand; the upper quadword
 is generated by moving two of the single-precision FP values from the source
 operand into the destination.
 The select (third) operand selects which of the values are moved to the
 destination register.
\layout Standard

The select operand is an 8-bit immediate: bits 0 and 1 select the value
 to be moved from the destination operand the low doubleword of the result,
 bits 2 and 3 select the value to be moved from the destination operand
 the second doubleword of the result, bits 4 and 5 select the value to be
 moved from the source operand the third doubleword of the result, and bits
 6 and 7 select the value to be moved from the source operand to the high
 doubleword of the result.
 
\layout Standard

SSE2-
\layout Itemize

CVTDQ2PS xmm, xmm
\layout Standard

Latency: 5 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Parallel convert signed dword integers to single precision floating point
 values
\layout Itemize

CVTPS2DQ xmm, xmm
\layout Standard

Latency: 5 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Parallel convert single precision floating point values to signed dword
 integers
\layout Itemize

CVTSD2SI r32, xmm 
\layout Standard

Latency: 8 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Convert double precision floating point value to integer qword (XMM only)
 
\layout Itemize

CVTPS2PD xmm, xmm 
\layout Standard

Latency: 10 Throughput: 4
\layout Standard

Purpose:
\layout Standard

Parallel convert single precision floating point values to double precision
 floating point values
\layout Itemize

CVTPD2PS xmm, xmm 
\layout Standard

Latency: 10 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Parallel convert double precision floating point values to single precision
 floating point values
\layout Itemize

CVTSS2SD xmm, xmm 
\layout Standard

Latency: 14 Throughput: 3
\layout Standard

Purpose:
\layout Standard

Convert single precision floating point value to double precision floating
 point value
\layout Itemize

CVTSD2SS xmm, xmm 
\layout Standard

Latency: 16 Throughput: 4
\layout Standard

Purpose:
\layout Standard

Convert double precision floating point value to single precision floating
 point value
\layout Itemize

PUNPCKHQDQ xmm1, xmm2/m128 
\layout Standard

Source: an XMM register or 128-bit memory location.
\layout Standard

Destination: an XMM register
\layout Standard

Latency: 4 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Interleaves the high quadword of the source operand and the high quadword
 of the destination operand and writes them to the destination register.
 The low quadwords of the source operands are ignored.
\layout Standard


\begin_inset Graphics
	filename images_sse2/NewPUNPCKLQDQ.gif
	lyxscale 55
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PUNPCKLQDQ xmm1, xmm2/m128 
\layout Standard

Source: an XMM register.
\layout Standard

Destination: an XMM register or 128-bit memory location.
\layout Standard

Latency: 4 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Interleaves the low quadwords of the source operand and the low quadwords
 of the destination operand and writes them to the destination register.
 The high quadwords of the source operands are ignored.
\layout Standard


\begin_inset Graphics
	filename images_sse2/NewPUNPCKHQDQ.gif
	lyxscale 55
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PSHUFHW xmm1, xmm2/m128, imm8 
\layout Standard

Source: unsigned doubleword integer stored in the low doubleword of an MMX
 register 
\layout Standard

or a 64-bit memory location, 
\layout Standard

or two packed unsigned doubleword integers in the first (low) and third
 doublewords of an XMM register 
\layout Standard

or an 128-bit memory location.
 
\layout Standard

Destination: an unsigned doubleword integer in the low doubleword an MMX
 register
\layout Standard

or two packed doubleword integers in the first and third doublewords of
 an XMM register.
 
\layout Standard

Latency: 2 Throughput: 2
\layout Standard

Purpose: