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PADDUSW Add Unsigned with Saturation on Word
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PADDUSW adds the unsigned words of the source operand to the unsigned words
 of the destination operand and stores the result in destination.
 If the result is larger than the range of an unsigned word (overflow),
 the value is saturated to 0FFFFh.
 If the result is smaller than the range of an unsigned word (underflow),
 the value is saturated to zero.
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPADDS.gif
	scale 55
	keepAspectRatio

\end_inset 


\layout Standard

SSE-
\layout Standard

Usage : instruction destination,source
\layout Itemize

ADDPS xmm1,xmm2/m128
\layout Standard

Latency : 4 Throughput : 2
\layout Standard

Purpose:
\layout Standard

Performs a SIMD add of the four packed single-precision floating-point values
 from the source operand (second operand) and the destination operand (first
 operand), and stores the packed single-precision floating-point results
 in the destination operand.
 The source operand can be an XMM register or a 128-bit memory location.
 The destination operand is an XMM register.
\layout Standard


\begin_inset Graphics
	filename images_sse/NewPADDPS.gif
	lyxscale 55
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

ADDSS xmm1, xmm2/m32
\layout Standard

Latency : 4 Throughput : 2
\layout Standard

Purpose:
\layout Standard

Adds the low single-precision floating-point values from the source operand
 (second operand) and the destination operand (first operand), and stores
 the single-precision floating-point result in the destination operand.
 The source operand can be an XMM register or a 32-bit memory location.
 The destination operand is an XMM register.
 The three high-order doublewords of the destination operand remain unchanged.
\layout Standard


\begin_inset Graphics
	filename images_sse/NewPADDSS.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Standard

SSE2-
\layout Itemize

ADDPD xmm, xmm
\layout Standard

Latency: 4 Throughput: 2 
\layout Standard

Purpose:
\layout Standard

Parallel add double precision floating point values
\layout Itemize

ADDSD xmm, xmm 
\layout Standard

Latency: 4 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Add double precision floating point value in lower 64 bits
\layout Subsubsection

Subtraction
\layout Standard

MMX-
\layout Standard

Usage: instruction destination, source 
\layout Standard

Destination: MMX register.
 
\layout Standard

Source: MMX register or 64-bit memory operand.
\layout Itemize

PSUBB Subtraction with Wrap-around on Byte
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSUBB subtracts the bytes of the source operand from the bytes of the destinatio
n operand and returns the result to destination.
 When the result is too large or too small to be represented in a byte,
 the result wraps around and the lower 8 bits are written to the destination
 register.
\layout Itemize

PSUBW Subtraction with Wrap-around on Word
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSUBW subtracts the words of the source operand from the words of the destinatio
n operand and returns the result to destination.
 When the result is too large or too small to be represented in a word,
 the result wraps around and the lower 16 bits are written to the destination
 register.
\layout Itemize

PSUBD Subtraction with Wrap-around on Doubleword
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSUBD subtracts the doublewords of the source operand from the doublewords
 of the destination operand and returns the result to destination.
 When the result is too large or too small to be represented in a doubleword,
 the result wraps around and the lower 32 bits are written to the destination
 register.
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPSUB.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PSUBSB Subtract Signed with Saturation on Byte
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSUBSB subtracts the signed bytes of the source operand from the signed
 bytes of the destination operand, and writes the results to the destination
 register.
 If the result is larger or smaller than the range of a signed byte, the
 value is saturated; in the case of an overflow - to 7Fh, and in the case
 of an underflow - to 80h.
\layout Itemize

PSUBSW Subtract Signed with Saturation on Word
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSUBSW subtracts the signed words of the source operand from the signed
 words of the destination operand, and writes the results to the destination
 register.
 If the result is larger or smaller than the range of a signed word, the
 value is saturated; in the case of an overflow - to 7FFFh, and in the case
 of an underflow - to 8000h.
\layout Itemize

PSUBUSB Subtract Unsigned with Saturation on Byte
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSUBUSB subtracts the bytes of the source operand from the bytes of the
 destination operand and writes the results to the destination register.
 If the result element is less than zero (a negative value), it is saturated
 to 00h.
\layout Itemize

PSUBUSW Subtract Unsigned with Saturation on Word
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PSUBUSW subtracts the words of the source operand from the words of the
 destination operand and writes the results to the destination register.
 If the result element is less than zero (a negative value), it is saturated
 to 0000h.
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPSUBS.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Standard

SSE-
\layout Itemize

SUBPS xmm1 xmm2/m128 
\layout Standard

Latency : 4 Throughput : 2
\layout Standard

Purpose:
\layout Standard

Performs a SIMD subtract of the four packed single-precision floating-point
 values in the source operand (second operand) from the four packed single-preci
sion floating-point values in the destination operand (first operand), and
 stores the packed single-precision floating-point results in the destination
 operand.
 The source operand can be an XMM register or a 128-bit memory location.
 The destination operand is an XMM register.
\layout Standard


\begin_inset Graphics
	filename images_sse/NewPSUBPS.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

SUBSS xmm1, xmm2/m32
\layout Standard

Latency : 4 Throughput : 2
\layout Standard

Purpose:
\layout Standard

Subtracts the low single-precision floating-point value in the source operand
 (second operand) from the low single-precision floating-point value in
 the destination operand (first operand), and stores the single-precision
 floating-point result in the destination operand.
 The source operand can be an XMM register or a 32-bit memory location.
 The destination operand is an XMM register.
 The three high-order doublewords of the destination operand remain unchanged.
\layout Standard


\begin_inset Graphics
	filename images_sse/NewPSUBSS.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Standard

SSE2-
\layout Itemize

SUBPD xmm, xmm 
\layout Standard

Latency: 4 Throughput: 2 
\layout Standard

Purpose:
\layout Standard

Parallel subtract double precision floating point values
\layout Itemize

SUBSD xmm, xmm 
\layout Standard

Latency: 4 Throughput: 2 
\layout Standard

Purpose:
\layout Standard

Subtract double precision floating point value in lower 64 bits
\layout Subsubsection

Multiplication
\layout Standard

MMX-
\layout Standard

Usage: instruction destination, source 
\layout Standard

Destination: MMX register.
 
\layout Standard

Source: MMX register or 64-bit memory operand.
\layout Itemize

PMULHW Packed Multiply High on Words
\layout Standard

Latency : 8 Throughput : 1
\layout Standard

Purpose:
\layout Standard

The PMULHW instruction multiplies the four signed words of the destination
 operand with the four signed words of the source operand.
 The high-order 16 bits of the 32-bit intermediate results are written to
 the destination operand.
\layout Itemize

PMULLW Packed Multiply Low on Words
\layout Standard

Latency : 8 Throughput : 1
\layout Standard

Purpose:
\layout Standard

The PMULLW instruction multiplies the four signed or unsigned words of the
 destination operand with the four signed or unsigned words of the source
 operand.
 The low-order 16 bits of the 32-bit intermediate results are written to
 the destination operand.
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPMUL.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

PMADDWD Packed Multiply and Add
\layout Standard

Latency : 8 Throughput : 1
\layout Standard

Purpose:
\layout Standard

The PMADDWD instruction multiplies the four signed words of the destination
 operand by the four signed words of the source operand.
 The result is two 32-bit doublewords.
 The two high-order words are summed and stored in the upper doubleword
 of the destination operand.
 The two low-order words are summed and stored in the lower doubleword of
 the destination operand.
 This result is written to the destination operand.
 
\layout Standard

The PMADDWD instruction wraps around to 80000000h only when all four words
 of both the source and destination operands are 8000h.
\layout Standard


\begin_inset Graphics
	filename images_mmx/NewPMADD.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Standard

SSE-
\layout Itemize

MULPS xmm1, xmm2/m128 
\layout Standard

Latency : 6 Throughput : 2
\layout Standard

Purpose:
\layout Standard

Performs a SIMD multiply of the four packed single-precision floating-point
 values from the source operand (second operand) and the destination operand
 (first operand), and stores the packed single-precision floating-point
 results in the destination operand.
 The source operand can be an XMM register or a 128-bit memory location.
 The destination operand is an XMM register.
\layout Standard


\begin_inset Graphics
	filename images_sse/NewPMULPS.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Itemize

MULSS xmm1, xmm2/m32 
\layout Standard

Latency : 6 Throughput : 2
\layout Standard

Purpose:
\layout Standard

Multiplies the low single-precision floating-point value from the source
 operand (second operand) by the low single-precision floating-point value
 in the destination operand (first operand), and stores the single-precision
 floating-point result in the destination operand.
 The source operand can be an XMM register or a 32-bit memory location.
 The destination operand is an XMM register.
 The three high-order doublewords of the destination operand remain unchanged.
\layout Standard


\begin_inset Graphics
	filename images_sse/NewPMULSS.gif
	lyxscale 65
	scale 55
	keepAspectRatio

\end_inset 


\layout Standard

SSE2-
\layout Itemize

MULPD xmm, xmm 
\layout Standard

Latency: 6 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Parallel multiply double precision floating point values
\layout Itemize

MULSS xmm, xmm 
\layout Standard

Latency: 6 Throughput: 2
\layout Standard

Purpose:
\layout Standard

Multiply double precision floating point value in lower 64 bits
\layout Subsection

Comparison Instructions
\layout Standard

MMX-
\layout Standard

Usage: instruction destination, source 
\layout Standard

Destination: MMX register.
 
\layout Standard

Source: MMX register or 64-bit memory operand.
\layout Itemize

PCMPEQB Packed Compare for Equal, Byte
\layout Standard

Latency : 2 Throughput : 1
\layout Standard

Purpose:
\layout Standard

PCMPEQB compares the bytes in the destination operand to the corresponding
 bytes in the source operand.
 If the data elements are equal, the corresponding data element in destination
 is set to all ones.
 If they are not equal, the corresponding data element is set to all zeros.