ics_554_test.c

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  board->blocks_per_frame = 100;
  board->block_count = 0;
  board->params[0]->addr_rx = swr_malloc( board->block_size * 
			       board->blocks_per_frame *
			       sizeof( u64 ) );
  if ( board->params[0]->addr_rx == NULL ){
    PR_DBG( 0, "Unable to allocate memory for board->data\n");
    return 0;
  }

  // Reset the board
  ics554_board_reset( board, 0, 0x3 );
  ics554_fifo_size( board, 0, 65536 - board->block_size - 2 );
  //  ics554_fifo_size( board, 0, 0xfe00 );
  ics554_decimation( board, 0 );

  // Setup the DDCs
  ics554_channel_count( board, 7, 0 );
  ics554_ddc_enable( board, 1 );
  
  for ( ddc=0; ddc<1; ddc++ ){
    ics554_ddc_select( board, ddc );

    // Setup the channels of the DDC
    for ( channel = 0; channel < 4; channel++ ){
      ics554_ddc_set_channel( board, channel, 1,
			      2, cfir_150, pfir_150, 
			      channel%2 ? 0xc000:0, 30,8 ,0 );
    }
    
    ics554_ddc_finalize( board, 4, res_9x32_60, 2 );
  }
  
  // Reset all other DDCs to 0
  for ( ddc=1; ddc<4; ddc++ ){
    ics554_ddc_select( board, ddc );
    for ( channel = 0; channel < 4; channel++ ){
      wr_ddc_page( channel * 8, 16, 0x80 );
    }
    wr_ddc( 0, 0x08 );
    wr_ddc( 5, 0x5c );
  }
  
  // Clean the DDC-selection
  ics554_ddc_deselect( board );
  
  ics554_adc_reset( board );
  ics554_enable( board, 1, 1 );
  clock_gettime( CLOCK_REALTIME, &tp );
  tp.tv_sec+=2;
  
  PR_DBG( 0, "Status: %x\n", ics554_status( board ) );
  // Prepare the interrupt and trigger the ADC
  pthread_mutex_lock( &int_554_mutex );
  ics554_trigger( board );

  t = gethrtime();
  for ( i=0; (i<1000)&&test_554_loop; i++ ){ 
    int count;
    u64 t_now;
    s32 *d32;
    clock_gettime( CLOCK_REALTIME, &tp );
    tp.tv_sec+=3;
/*     if ( pthread_cond_timedwait( &int_554_cond, &int_554_mutex, &tp ) ){ */
/*       pthread_mutex_unlock( &int_554_mutex ); */
/*       PR_DBG( 0, "Time-out while waiting for the ADC...\n" ); */
/*       return 0; */
/*     } */
    usleep( 300000 );

    t_now = gethrtime();
    PR_DBG( 4, "Block %5i, time: %i\n", (u32)board->block_count,
	    ( t_now - t ) / 1000 );

    // Always take the first block
    d32 = (s32*)board->params[0]->addr_rx + board->block_size * 0;
#if 1
    // Show what we got from the DMA
    for( count = 0; count < 50; count++){
      int re, im, a;
      re = d32[ count * 2 ] >> 8;
      im = d32[ count * 2 + 1 ] >> 8;
      a = hypot( re, im );
      PR_DBG(0,"Data[%4x] = %8i, %8i = |%8i|\n", count,
	     re, im, a );
      // Wait a bit so that the syslogger can do it's job
      rtl_udelay( 100 );
    }
#endif
#if 0
    show_dft( d32, dft_len, board->block_count > 100000 );
#endif
    PR_DBG( 4, "Block %5i, time: %i\n", board->block_count,
	    ( gethrtime() - t ) / 1000 );
  }

  board->flags |= ICS554_NO_INT;
  swr_free( board->params[0]->addr_rx );
  ics554_reset( board );
  return NULL;
}



// Captures some data at the full rate and downconverts using the 
// graychip
void *test_down_gray_multi_cont( void *arg ){
  struct ics_dev *board = arg;
  short i;
  short channel, ddc;
  struct timespec tp;
  u64 t;

  board->flags |= ICS554_INT_BROADCAST;
  // Get some data-space
  board->block_size = 0x8000;
  board->blocks_per_frame = 20;
  board->block_count = 0;
  board->params[0]->addr_rx = swr_malloc( board->block_size * 
			       board->blocks_per_frame *
			       sizeof( u64 ) );
  if ( board->params[0]->addr_rx == NULL ){
    PR_DBG( 0, "Unable to allocate memory for board->data\n");
    return 0;
  }

  // Reset the board
  ics554_board_reset( board, 0, 0x3 );
  ics554_fifo_size( board, 0, 65536 - board->block_size - 2 );
  //  ics554_fifo_size( board, 0, 0xfe00 );
  ics554_decimation( board, 0 );
  ics554_acq_count( board, board->block_size );

  // Setup the DDCs
  ics554_channel_count( board, 15, 0 );
  ics554_ddc_enable( board, 1 );
  
  for ( ddc=1; ddc>=0; ddc-- ){
    ics554_ddc_select( board, ddc );

    // Setup the channels of the DDC
    for ( channel = 0; channel < 4; channel++ ){
      ics554_ddc_set_channel( board, channel, ddc,
			      2, cfir_17, pfir_17, 
			      channel%2 ? 0xc000:0, 30 + ddc * 2,8 ,0 );
    }

    ics554_ddc_finalize( board, 5, res_9x32_60, 2 );
  }

  // Reset all other DDCs to 0
/*   for ( ddc=2; ddc<4; ddc++ ){ */
/*     ics554_ddc_select( board, ddc ); */
/*     for ( channel = 0; channel < 4; channel++ ){ */
/*       wr_ddc_page( channel * 8, 16, 0x80 ); */
/*     } */
/*     ics554_ddc_finalize( board, 0, 0, 0 ); */
/*   } */

  // Clean the DDC-selection
  ics554_ddc_deselect( board );

  ics554_adc_reset( board );
  ics554_enable( board, 1, 1 );
  clock_gettime( CLOCK_REALTIME, &tp );
  tp.tv_sec+=2;
  
  PR_DBG( 0, "Status: %x\n", ics554_status( board ) );
  // Prepare the interrupt and trigger the ADC
  pthread_mutex_lock( &int_554_mutex );
  ics554_trigger( board );

  t = gethrtime();
  for ( i=0; (i<1000)&&test_554_loop; i++ ){ 
    int j;
    u64 t_now;
    s32 *d32;
    clock_gettime( CLOCK_REALTIME, &tp );
    tp.tv_sec+=3;
    for ( j=0; j<40; j++ ){
      if ( pthread_cond_timedwait( &int_554_cond, &int_554_mutex, &tp ) ){
	pthread_mutex_unlock( &int_554_mutex );
	PR_DBG( 0, "Time-out while waiting for the ADC...\n" );
	return 0;
      }
    }

    t_now = gethrtime();
    PR_DBG( 4, "Block %5i, time: %i\n", (u32)board->block_count,
	    ( t_now - t ) / 1000 );

    // Always take the first block
    d32 = (s32*)board->params[0]->addr_rx;
#if 1
    {
      int count;
      // Show what we got from the DMA
      for( count = 0; count < 80; count++){
	int re, im;
/* 	int index = count / 4 * 8 * 2 + ( count % 4 ) * 2; */
/* 	re1 = d32[ index ] >> 8; */
/* 	re2 = d32[ index + 4 * 2 ] >> 8; */
	int index = count * 2;
	if ( count % 8 >= 4 ){
	  re = d32[ index ] >> 8;
	  im = d32[ index + 1 ] >> 8;
	  PR_DBG(0,"Data[%4x] = %8i, %8i = |%8i|\n", index,
		 re, im, (int)hypot( re, im ) );
	  // Wait a bit so that the syslogger can do it's job
	  rtl_udelay( 50 );
	}
      }
    }
#endif
#if 0
    {
      int dft_len=23;
      int count;
      s32 d_ch[2][dft_len * 2];
      for ( count=0; count<dft_len * 2; count++ ){
	int index = ( count / 8 ) * 16 + count % 8;
	d_ch[0][count] = d32[ index + 1 * 8];
	d_ch[1][count] = d32[ index + 0 * 8];
      }
      PR_DBG( 0, "Channel 0\n" );
      show_dft( d_ch[0], dft_len, 0 * board->block_count > 100 );
      PR_DBG( 0, "Channel 1\n" );
      show_dft( d_ch[1], dft_len, 0 * board->block_count > 100 );
    }
#endif
    PR_DBG( 4, "Block %5i, time: %i\n", (u32)board->block_count,
	    ( gethrtime() - t ) / 1000 );
  }

  board->flags |= ICS554_NO_INT;
  swr_free( board->params[0]->addr_rx );
  ics554_reset( board );
  return NULL;
}



// Captures some data at the full rate and downconverts using the 
// graychip
void *test_down_gray_quad_cont( void *arg ){
  struct ics_dev *board = arg;
  short i;
  short channel, ddc;
  struct timespec tp;
  u64 t;

  // Get some data-space
  board->block_size = 0x8000;
  board->blocks_per_frame = 20;
  board->block_count = 0;
  board->params[0]->addr_rx = swr_malloc( board->block_size * 
			       board->blocks_per_frame *
			       sizeof( u64 ) );
  if ( board->params[0]->addr_rx == NULL ){
    PR_DBG( 0, "Unable to allocate memory for board->data\n");
    return 0;
  }
  board->params[1]->addr_rx = swr_malloc( board->block_size * 
					  board->blocks_per_frame *
					  sizeof( u64 ) );
  if ( board->params[1]->addr_rx == NULL ){
    PR_DBG( 0, "Unable to allocate memory for board->data\n");
    swr_free( board->params[0]->addr_rx );
    return 0;
  }

  // Reset the board
  ics554_board_reset( board, 0, 0x3 );
  ics554_fifo_size( board, 0, 65536 - board->block_size - 2 );
  ics554_fifo_size( board, 1, 65536 - board->block_size - 2 );
  ics554_decimation( board, 0 );
  ics554_acq_count( board, board->block_size );

  // Setup the DDCs
  ics554_channel_count( board, 15, 15 );
  ics554_ddc_enable( board, 3 );
  
  for ( ddc=3; ddc>=0; ddc-- ){
    ics554_ddc_select( board, ddc );

    // Setup the channels of the DDC
    for ( channel = 0; channel < 4; channel++ ){
      ics554_ddc_set_channel( board, channel, 1,
			      2, cfir_68, pfir_68,
			      channel%2 ? 0xc000:0, 30 + ddc * 0 ,8,0);
    }

    ics554_ddc_finalize( board, 6, res_9x32_60, 2 );

    // Clean the DDC-selection
    ics554_ddc_deselect( board );
  }

  ics554_adc_reset( board );
  ics554_enable( board, 3, 1 );
  clock_gettime( CLOCK_REALTIME, &tp );
  tp.tv_sec+=2;
  
  PR_DBG( 0, "Status: %x\n", ics554_status( board ) );
  // Prepare the interrupt and trigger the ADC
  pthread_mutex_lock( &int_554_mutex );
  ics554_trigger( board );

  pthread_make_periodic_np( pthread_self(), gethrtime(), 1000*1000*50 );
  t = gethrtime();
  for ( i=0; (i<10000)&&test_554_loop; i++ ){ 
    u64 t_now;
    s32 *d32;
    clock_gettime( CLOCK_REALTIME, &tp );
    tp.tv_sec+=3;
    pthread_wait_np();

    t_now = gethrtime();
    PR_DBG( 4, "Block %5i, time: %i\n", (u32)board->block_count,
	    ( t_now - t ) / 1000 );

    // Always take the first block
#if 1
    {
      int count;
      // Show what we got from the DMA
      for ( ddc = 0; ddc < 4; ddc++ ){
	d32 = (s32*)board->params[ddc / 2]->addr_rx;
	PR_DBG( 0, "DDC %i gives\n", ddc );
	for( count = 0; count < 8; count++){
	  int re, im;
	  int index = ( ddc % 2 ) * 8 + 
	    count * 2 + ( ( count / 4 ) * 8 );
	  re = d32[ index ] >> 8;
	  im = d32[ index + 1 ] >> 8;
	  PR_DBG(0,"Data[%4x] = %8i, %8i = |%8i|\n", index,
		 re, im, (int)hypot( re, im ) );
	  // Wait a bit so that the syslogger can do it's job
	  rtl_udelay( 50 );
	}
      }
    }
#endif
#if 0
    {
      int dft_len=9;
      int count;
      for ( ddc = 0; ddc < 4; ddc++ ){
	int data[dft_len * 2];
	d32 = (s32*)board->params[ddc / 2]->addr_rx;
	PR_DBG( 0, "DDC %i gives\n", ddc );
	for( count = 0; count < 9; count++){
	  int index = ( ddc % 2 ) * 8 + 
	    count * 2 + ( ( count / 4 ) * 8 );
	  data[2*count] = d32[ index ];
	  data[2*count+1] = d32[ index + 1 ];
	}
	show_dft( data, dft_len, 0 );
      }
    }
#endif
    t_now = gethrtime();
    PR_DBG( 4, "Block %5i, time: %i, time/block:%i\n", (u32)board->block_count,
	    ( t_now - t ) / 1000,
	    ( t_now - t ) / board->block_count );
  }

  board->flags |= ICS554_NO_INT;
  swr_free( board->params[0]->addr_rx );
  swr_free( board->params[1]->addr_rx );
  ics554_reset( board );
  return NULL;
}



void *test_module( void *arg ){
  struct ics_dev *board = arg;
  int ch, i, t, nbr_ch = 4,
    bpf = 20;
  // ADC 0 and 1 go into data[0]
  // ADC 2 and 3 go into data[1]
  s32 *data[ nbr_ch / 2 + 1 ];

  // Initialise all channels
  for ( i=0; i<nbr_ch; i++ ){
    if ( !( i % 2 ) ){
      data[ i / 2 ] = swr_malloc( board->block_size * bpf *
			      sizeof( u64 ) );
      // We could be out of memory
      if ( !data[ i / 2 ] ){
	PR_DBG( 0, "Couldn't get %ikB of memory.\n",
		board->block_size * bpf * sizeof( u64 ) / 1024 );
	for ( i--; i>= 0; i-- ){
	  swr_free( data[ i / 2 ] );
	}
	return NULL;
      }
    }

    // Or get the channels in a strange order
    if ( swr_ant_ch_init( board_params_554 + i ) != i ){
      PR_DBG( 0, "Couldn't get antenna in order!\n" );
      return 0;
    }
    board_params_554[i].addr_rx = data[ i / 2 ];
    board_params_554[i].frame_blocks = bpf;
  }

  // OK, let's start
  swr_ant_ch_start( );

  t = 0;
  pthread_make_periodic_np( pthread_self(), gethrtime(), 1000*1000*100 );
  while ( test_554_loop ){
    pthread_wait_np();
    PR_DBG( 0, "Still looping: %6i blocks and %i seconds\n", 
	    board->block_count, t++ );
    for ( ch=0; ch<nbr_ch; ch++ ){
      PR_DBG( 0, "------------- Channel %i:\n", ch );
#if 0
      for ( i=0; i<16; i++ ){
	PR_DBG( 0, "Data[%x] = %5i + i*%5i\n", i,
		data[ch][ 2 * i ] >> 8, data[ch][ 2 * i + 1 ] >> 8 );
	rtl_udelay( 50 );
      }
      rtl_udelay( 1000 );
#endif
#if 1
      {
	int dft_len=9;
	int count;
	int d[dft_len * 2];
	for( count = 0; count < dft_len; count++){
	  int index = ( ch % 2 ) * 8 + 
	    count * 2 + ( ( count / 4 ) * 8 );
	  d[2*count] = data[ch / 2][ index ];
	  d[2*count+1] = data[ch / 2][ index + 1 ];
	}
	show_dft( d, dft_len, 0 );
      }
#endif
    }
  }

  PR_DBG( 1, "Stopping the antennas\n" );
  swr_ant_ch_stop();

  PR_DBG( 1, "Freeing the memory\n" );
  for ( i=0; i<nbr_ch; i+=2 ){
    swr_free( data[ i/2 ] );
  }

  return NULL;
}



struct thread test_554;
void ics554_test_start( struct ics_dev *board ){
  int i;

  for ( i=0; i<ADA_PER_BOARD; i++ ){
    board_rx.params[ i ] = board_params_554 + i;
    board_rx.params[ i ]->addr_rx = NULL;
  }

  board->flags |= ICS554_STARTED | ICS554_TEST;
  board->flags &= ~ICS554_INT_DMA;
  test_554_loop = 1;
  switch( 8 ){
  case 0:
    board->flags |= ICS554_NO_INT;
    swr_thread_init( &test_554, test_capture, board );
    break;
  case 1:
    swr_thread_init( &test_554, test_capture_int, board );
    break;
  case 2:
    board->flags |= ICS554_NO_INT;
    swr_thread_init( &test_554, test_capture_bichannel, board );
    break;
  case 3:
    swr_thread_init( &test_554, test_thread, board );
    break;
  case 4:
    swr_thread_init( &test_554, test_down_gray_simple, board );
    break;
  case 5:
    swr_thread_init( &test_554, test_down_gray, board );
    break;
  case 6:
    // Ne marche pas ?!?
    board->flags |= ICS554_INT_DMA;
    swr_thread_init( &test_554, test_down_gray_cont, board );
    break;
  case 7:
    // Marche pas non plus
    board->flags |= ICS554_INT_DMA;
    swr_thread_init( &test_554, test_down_gray_multi_cont, board );
    break;
  case 8:
    board->flags |= ICS554_INT_DMA;
    swr_thread_init( &test_554, test_down_gray_quad_cont, board );
    break;
  case 9:
    board->flags |= ICS554_INT_DMA;
    swr_thread_init( &test_554, test_module, board );
    break;
  }

  return;
}

void ics554_test_stop( struct ics_dev *board ){

  PR_DBG( 1, "Cancelling test\n" );
  test_554_loop = 0;
  PR_DBG( 1, "Freeing test\n" );
  swr_thread_free( &test_554, NULL );
  
  PR_DBG( 1, "Freed thread and memory\n" );

  swr_memory_show();
}