ics_554.c

软件无线电的平台

/***************************************************************************
             ics_554.c  -  ICS-554 driver
                            -------------------
    begin                :  2003
    authors              :  Linus Gasser
    emails               :  [e-mail]
 ***************************************************************************/

/***************************************************************************
                                 Changes
                                 -------
 date - name - description
 03-09-16 - ineiti - create

 **************************************************************************/

/***************************************************************************
 *                                                                         *
 *    This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 ***************************************************************************/
#include "system.h"
#include "ics_554.h"
#include "ics_554_test.h"
#include "ql_5064.h"
#include <linux/pci.h>
#include "debugging.h"
#include <math.h>
#include "std.h"
#include "rtl_time.h"
#include "filters.h"
#include <time.h>

pthread_cond_t int_554_cond = PTHREAD_COND_INITIALIZER;
pthread_mutex_t int_554_mutex = PTHREAD_MUTEX_INITIALIZER;

#define DBG_LVL 0
// 0 means to send the CLK
#define CLOCK_INPUT 1

void adc_start_dma( struct ics_dev *board, u64 dac, void *to, u64 count ){

  //FIFO1 assumed - use the FROM parameter to denote FIFO1, FIFO2
  WRITE_QL5064_U64( board, FROMICS_PCI_ADDR, virt_to_bus( to ) );
  WRITE_QL5064_U64( board, FROMICS_COUNT, count );
  WRITE_QL5064_U64( board, LOC_XMT0_CNT_ADDR, ( count << 32 ) +
		    0x800000 * dac ); 
  WRITE_QL5064_U64( board, DMA_CONTROL, DMA_START_FROMICS );
  PR_DBG( 3, "Started DMA for dac %lli and %lli bytes\n", dac, count );
}


void adc_cancel_dma( struct ics_dev *board ){
  WRITE_QL5064_U8( board, LOC_DMA_CANCEL, 1 );
}


u16 ics554_status( struct ics_dev *board ){
  return READ_ICS554_U16( board, STATUS );
}


void ics554_fifo_size( struct ics_dev *board, u32 fifo, u32 paf ){
  int i;
  u32 cr2 = READ_ICS554_U32( board, CONTROL2 ) & ~0x3;

  WRITE_ICS554_U32( board, CONTROL2, cr2 | ( 1 << ( fifo & 1 ) ) );
  rtl_udelay( 1000 );

  paf <<= 16;
  paf += 0xffff;
  for ( i=0; i<32; i++ ){
    WRITE_ICS554_U32( board, FIFO, paf & 1 );
    rtl_udelay( 100 );
    paf >>= 1;
  }
  // Reset the control2 register w/o the first two bits.
  WRITE_ICS554_U32( board, CONTROL2, cr2 & ~0x3 );
  
  rtl_udelay( 1000 );
}


void ics554_board_reset( struct ics_dev *board, u32 single, u32 reverse ){
  single &= 3;
  reverse &= 3;

  // Single Channel mode
  WRITE_ICS554_U32( board, CONTROL1, ( single << 8 ) | CLOCK_INPUT );
  // Board Reset; clears CR's except set above
  WRITE_ICS554_U32( board, SOFT_BOARD_RESET, 1); 
  // Reverse FIFO ordering
  WRITE_ICS554_U32( board, CONTROL2, reverse << 8 );
  
  rtl_udelay( 10000 );
}


void ics554_decimation( struct ics_dev *board, u32 rate ){
  // Set Decimation, if fact this does not work... 
  // see void ics554_ddc_set_cic()
  WRITE_ICS554_U32( board, ADC_CH12_DEC, rate );
  WRITE_ICS554_U32( board, ADC_CH34_DEC, rate );

  rtl_udelay( 10000 );
}

void ics554_acq_count( struct ics_dev *board, u32 count ){
  WRITE_ICS554_U32( board, ADC_CH12_ACQ, count );
  WRITE_ICS554_U32( board, ADC_CH34_ACQ, count );
}

void ics554_capture( struct ics_dev *board, u32 count ){

  // Single Channel mode + capture
  WRITE_ICS554_U32( board, CONTROL1, 
		    READ_ICS554_U32( board, CONTROL1 ) | 0x10 | CLOCK_INPUT );
  ics554_acq_count( board, count );
  rtl_udelay( 10000 );
}


void ics554_adc_reset( struct ics_dev *board ){
  // Reset ADC
  WRITE_ICS554_U32( board, SOFT_ADC_RESET, 0x1);
 
  rtl_udelay( 10000 );
}


void ics554_imr( struct ics_dev *board, u32 imr ){
  WRITE_ICS554_U32( board, IRQ_MASK, imr );
}


void ics554_enable( struct ics_dev *board, u32 adc, u32 imr ){
  u32 cr1 = READ_ICS554_U32( board, CONTROL1 ) & ~0xc0;
  adc &= 3;

  // Set enable bit in Control register 
  WRITE_ICS554_U32( board, CONTROL1, cr1 | ( adc << 6 ) | CLOCK_INPUT );

  // Enable Interrupt
  ics554_imr( board, imr );
}


void ics554_trigger( struct ics_dev *board ){
  // Write to Trigger Register
  WRITE_ICS554_U32( board, TRIGGER, 0x1);
}


void ics554_channel_count( struct ics_dev *board, u32 cc12, u32 cc34 ){
  WRITE_ICS554_U32( board, CHANNEL_COUNT, 
		    ( cc12 & 0xf ) + ( ( cc34 & 0xf ) << 4 ) );
  
  rtl_udelay( 10000 );
}


void ics554_ddc_enable( struct ics_dev *board, u32 ddc ){
  u32 cr2 = READ_ICS554_U32( board, CONTROL2 ) & ~0xc;
  ddc &= 3;

  WRITE_ICS554_U32( board, CONTROL2, cr2 | ( ddc << 2 ) );
  
  rtl_udelay( 1000 );
}


void ics554_ddc_select( struct ics_dev *board, u32 ddc ){
  u32 cr2 = READ_ICS554_U32( board, CONTROL2 ) & ~0xf0;
  ddc &= 3;

  WRITE_ICS554_U32( board, CONTROL2, cr2 | ( 0x10 << ddc ) );

  rtl_udelay( 1000 );
  wr_ddc( 0, 0xf8 );
  wr_ddc( 1, 0x00 );
  wr_ddc( 4, 0x27 );
  wr_ddc( 5, 0xd0 );
  wr_ddc( 6, 0x00 );
  wr_ddc( 7, 0x00 );
  
  rtl_udelay( 1000 );
}


void ics554_ddc_deselect( struct ics_dev *board ){
  WRITE_ICS554_U32( board, CONTROL2, 
		    READ_ICS554_U32( board, CONTROL2 ) & ~0xf0 );
  
  rtl_udelay( 1000 );
}

u8 ddc_act_page;
void ics554_ddc_write( struct ics_dev *board, u8 page, u8 offset, u8 data ){
  if ( page != ddc_act_page ){
    WRITE_GC4016( board, 2, page << 1 );
    rtl_udelay( 100 );
    ddc_act_page = page;
  }
  WRITE_GC4016( board, offset, data );
}


u8 ics554_ddc_read( struct ics_dev *board, u8 page, u8 offset ){
  WRITE_GC4016( board, 2, page << 1 );
  return READ_GC4016( board, offset );
}


// Channel control page 7,
// Addresses: 0x10 (Channel Reset)  --> 0x1F (Fine Gain Byte 1)


// index:
// 0 - first try, from ICS
// 1 - umts-example
// 2 - our try

void ics554_ddc_set_ccp( struct ics_dev *board, u32 channel, u8 index ){
  u8 data[][16] = { 
    // first try
    { 0x0c, 0x77, 0x22, 0x20, 
      0x22, 0x07, 0x70, 0x79,
      0x00, 0x00, 0x00, 0x00,
      0x1d, 0x00, 0x00, 0x04 },
    // wideband original
    { 0x0c, 0x77, 0x22, 0x20,
      0x22, 0x07, 0x70, 0x7d,
      0x30, 0x10, 0x06, 0x00,
      0x1d, 0x00, 0x30, 0x09 },
    // wideband merged
    { 0x0c, 0x77, 0x22, 0x20, 
      0x22, 0x07, 0x70, 0x79,
      0x00, 0x00, 0x00, 0x00,
      0x1d, 0x00, 0x00, 0x04 },
    // simple
    { 0x0c, 0x77, 0x22, 0x20, 
      0x22, 0x07, 0x70, 0x79,
      0x00, 0x00, 0x00, 0x00,
      0x1d, 0x00, 0x00, 0x04 },
    // wideband cutted
    { 0x0c, 0x77, 0x22, 0x20, 
      0x22, 0x0f, 0x70, 0x79,
      0x00, 0x00, 0x00, 0x00,
      0x1d, 0x00, 0x00, 0x04 },
    // GPS
    { 0x0e, 0x77, 0x22, 0x20,  // 0x10, 0x11, 0x12, 0x13 
      0x22, 0x07, 0x70, 0x79,  // 0x14, 0x15, 0x16, 0x17 
      0x00, 0x70, 0x00, 0x00,  // 0x18, 0x19, 0x1A, 0x1B 
      0x00, 0x00, 0x00, 0x00 },// 0x1C, 0x1D, 0x1E, 0x1F 
  };
  u8 ch[][4][3] = {
    { { 0x00, 0x00, 0x00 },
      { 0x00, 0x00, 0x00 },
      { 0x00, 0x00, 0x00 },
      { 0x00, 0x00, 0x00 } },
    { { 0x30, 0x10, 0x06 },
      { 0x50, 0x10, 0x06 },
      { 0x30, 0x10, 0x00 },
      { 0x50, 0x10, 0x00 } },
    { { 0x30, 0x00, 0x02 },
      { 0x50, 0x00, 0x02 },
      { 0x30, 0x00, 0x00 },
      { 0x50, 0x00, 0x00 } },
    { { 0x00, 0x00, 0x00 },
      { 0x00, 0x00, 0x00 },
      { 0x00, 0x00, 0x00 },
      { 0x00, 0x00, 0x00 } },
    { { 0x30, 0x00, 0x02 },
      { 0x50, 0x00, 0x02 },
      { 0x30, 0x00, 0x00 },
      { 0x50, 0x00, 0x00 } },
    { { 0x30, 0x00, 0x02 },
      { 0x50, 0x00, 0x02 },
      { 0x30, 0x00, 0x00 },
      { 0x50, 0x00, 0x00 } },
  };
  u8 page = ( channel & 3 ) * 8 + 7;
  u8 offset;

  // Overwrite non-zero parameters
  for ( offset=0; offset<3; offset++ ){
    if ( ch[index][channel][offset] ){
      data[index][offset+8] = ch[index][channel][offset];
    }
  }

  PR_DBG( 4, "Channel: %i ", channel );
  for ( offset=0x10; offset<0x20; offset++ ){
    u8 d = data[index][ offset - 0x10 ];
    wr_ddc_page( page, offset, d );
    PR_DBG_CL( 4, "[%2x]=%2x, \n", offset, (u32)d );
  }
  PR_DBG_CL( 4, "\n" );
}


void ics554_ddc_set_resampler( struct ics_dev *board, u8 index ){
  u8 data40[][8] = { //ie 0x40
    // first try
    { 0x23, 0x46, 0x00, 0x35,
      0xe4, 0x70, 0x00, 0x00 },
    // umts example 1
    { 0x20, 0x07, 0x00, 0x14,
      0x00, 0x70, 0x00, 0x00 },
    // umts example 2
    { 0x20, 0x48, 0x00, 0x33,
      0x00, 0x70, 0x00, 0x00 },
    // simple example
    { 0x23, 0x46, 0x00, 0x35,
      0xe4, 0x70, 0x00, 0x00 },
    // continous sampling
    { 0x20, 0x48, 0x00, 0x33,
      0x00, 0x70, 0x00, 0x00 },
    // continous sampling for multi-channels
    { 0x20, 0x48, 0x00, 0x33,
      0x00, 0x70, 0x00, 0x00 },
    // Sampling for quad-channels
    { 0x20, 0x48, 0x00, 0x33,
      0x00, 0x70, 0x00, 0x00 },
    // Sampling for dual-channels
    { 0x20, 0x48, 0x00, 0x33,
      0x05, 0x70, 0x00, 0x00 },
    // continous sampling for 10 kHz BW AM
    { 0x20, 0x48, 0x00, 0x33,
      0x00, 0x70, 0x00, 0x00 },
     // continous sampling for quad-channels GPS
    { 0x20, 0x48, 0x00, 0x35,
      0x00, 0x70, 0x00, 0x00 },
    // continous sampling for testos
    { 0x20, 0x48, 0x00, 0x33,
      0x00, 0x70, 0x00, 0x00 },
  };
  u8 data41[][16] = {
    { 0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04 },
    { 0x00, 0x00, 0x00, 0x02,
      0x00, 0x00, 0x00, 0x02,
      0x00, 0x00, 0x00, 0x02,
      0x00, 0x00, 0x00, 0x02 },
    { 0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04 },
    { 0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04 },
    { 0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04,
      0x00, 0x00, 0x00, 0x04 },
    { 0x00, 0x00, 0x00, 0x08,
      0x00, 0x00, 0x00, 0x08,
      0x00, 0x00, 0x00, 0x08,
      0x00, 0x00, 0x00, 0x08 },
#define DOWNCONVERT_6 (4<<2)
    { 0x00, 0x00, 0x00, DOWNCONVERT_6,
      0x00, 0x00, 0x00, DOWNCONVERT_6,
      0x00, 0x00, 0x00, DOWNCONVERT_6,
      0x00, 0x00, 0x00, DOWNCONVERT_6 },
#define DOWNCONVERT_7 (4<<2)
    { 0x00, 0x00, 0x00, DOWNCONVERT_7,
      0x00, 0x00, 0x00, DOWNCONVERT_7,
      0x00, 0x00, 0x00, DOWNCONVERT_7,
      0x00, 0x00, 0x00, DOWNCONVERT_7 },
    // AM 10kHz BW was 0x8
    { 0x00, 0x00, 0x00, 0x8,
      0x00, 0x00, 0x00, 0x8,
      0x00, 0x00, 0x00, 0x8,
      0x00, 0x00, 0x00, 0x8 },
    //GPS=9:ratio=5 this should work now for the GPS
    { 0x00, 0x00, 0x00, 0x08,
      0x00, 0x00, 0x00, 0x08,
      0x00, 0x00, 0x00, 0x08,
      0x00, 0x00, 0x00, 0x08},
    // testos=10 was 0x8
    { 0x00, 0x00, 0x00, 0x50,
      0x00, 0x00, 0x00, 0x50,
      0x00, 0x00, 0x00, 0x50,