rf_eeprom.c

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/***************************************************************************
             rf_eeprom.c  -  To program the EEPROM
                            -------------------
    begin                :  2003
    authors              :  Linus Gasser
    emails               :  [e-mail]
 ***************************************************************************/

/***************************************************************************
                                 Changes
                                 -------
 date - name - description
 03-02-21 - ineiti - create
 
 **************************************************************************/

/***************************************************************************
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 ***************************************************************************/


#define DBG_LVL 4
#define EXPORT_SYMTAB

#include "debugging.h"
#include "system.h"
#include "rf_io.h"
#include "rf_dev.h"

// The original length is 0x22
#define EEPROM_LENGTH 0x22

unsigned short eedata[] = {
                            0x9080,    // Device ID
                            0x10B5,    // Vendor ID
                            0x0680,    // Class Code
                            0x0002,    // Class Code Revision
                            0x3010,    // Max Latency, Min Grant
                            0x0100,    // Interrupt Pin, Interrupt Line Routing
                            0x0000,    // MSW of Mailbox 0
                            0x0000,    // LSW of Mailbox 0

                            0x0000,    // MSW of Mailbox 1
                            0x0000,    // LSW of Mailbox 1
                            0xFF00,    // MSW of range for PCI to Local Address Space 0 (16 MBytes)
                            0x0000,    // LSW of range for PCI to Local Address Space 0 (16 MBytes)
                            0xC000,    // MSW of Local Base Address (Re-Map) for PCI to Local Address Space 0
                            0x0001,    // LSW of Local Base Address (Re-Map) for PCI to Local Address Space 0
                            0x0000,    // Not Used
                            0x0000,    // Not Used


                            0x0000,    // Not Used
                            0x0000,    // Not Used
                            0xFFFF,    // MSW of Range for PCI to Local Expansion ROM
                            0x0000,    // LSW of Range for PCI to Local Expansion ROM
                            0xD000,    // MSW of Local Base Address (Re-Map) for PCI to Local Expansion ROM
                            0x0001,    // LSW of Local Base Address (Re-Map) for PCI to Local Expansion ROM
                            0x4004,    // MSW of Bus Region Descriptors for PCI to Local Accesses
                            0x0007,    // LSW of Bus Region Descriptors for PCI to Local Accesses

                            0x0000,    // MSW of Range for Direct Master to PCI
                            0x0000,    // LSW of Range for Direct Master to PCI
                            0x0000,    // MSW of Local Base Address for Direct Master to PCI Memory
                            0x0000,    // LSW of Local Base Address for Direct Master to PCI Memory
                            0x0000,    // MSW of Local Base Address for Direct Master to PCI IO/CFG
                            0x0000,    // LSW of Local Base Address for Direct Master to PCI IO/CFG
                            0x0000,    // MSW of PCI Base Address (Re-Map) for Direct Master to PCI
                            0x0000,    // LSW of PCI Base Address (Re-Map) for Direct Master to PCI

                            0x0000,    // MSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG
                            0x0000};    // LSW of PCI Configuration Address Register for Direct Master to PCI IO/CFG

#define EEREG ( addr + 0x006C )

#define EECLK_BIT 24
#define EECS_BIT  25
#define EEWR_BIT  26
#define EERD_BIT  27
#define EERELO_BIT  29
#define EECLK_LOW outl(inl(EEREG) & (~(1<<EECLK_BIT)),EEREG)


/* number of bits in eeprom register address */

#define EEPROM_ALEN 6


/**
 * Write a bit to the eeprom
 */
void eeprom_wbit( unsigned int addr, int bit ) {

  /* set data  */
  if (bit) {
    outl(inl(EEREG) | (1<<EEWR_BIT),EEREG);
  } else {
    outl(inl(EEREG) & ~(1<<EEWR_BIT),EEREG);
  }

  /* set clock high */
  outl(inl(EEREG) | (1<<EECLK_BIT),EEREG);
  /* set clock low */
  outl(inl(EEREG) & (~(1<<EECLK_BIT)),EEREG);
}


/**
 * Read a bit to the eeprom
 */
int eeprom_rbit( unsigned int addr ) {
  int bit=0;

  /* set clock high */
  outl(inl(EEREG) | (1<<EECLK_BIT),EEREG);
  /* set clock low  */
  outl(inl(EEREG) & (~(1<<EECLK_BIT)),EEREG);

  if (inl(EEREG)&(1<<EERD_BIT)) {
    bit=1;
  }

  return bit;
}


/**
 * enable all programming modes 
 */
void eeprom_wen( unsigned int addr ) {
  int i;

  /* set clock low  */
  outl(inl(EEREG) & (~(1<<EECLK_BIT)),EEREG);

  /* set cs  */
  outl(inl(EEREG) | (1<<EECS_BIT),EEREG);

  eeprom_wbit( addr, 1 );
  eeprom_wbit( addr, 0 );
  eeprom_wbit( addr, 0 );

  for(i=0; i<EEPROM_ALEN; i++) {
    eeprom_wbit( addr, 1 );
  }

  /* reset cs  */
  outl(inl(EEREG) & (~(1<<EECS_BIT)),EEREG);


}

/*
 * write the specified eeprom register 
 */

void eeprom_wreg( unsigned int addr, int reg, int data) {

  int i;

  /* make sure writing is enabled */
  /* eeprom_wen(); */

  /* set clock low  */
  outl(inl(EEREG) & (~(1<<EECLK_BIT)),EEREG);

  /* set cs  */
  outl(inl(EEREG) | (1<<EECS_BIT),EEREG);

  /* Write Register Command */
  eeprom_wbit( addr, 1 );
  eeprom_wbit( addr, 0 );
  eeprom_wbit( addr, 1 );

  /* write address MSB first */
  for(i=(EEPROM_ALEN-1); i>=0; i--) {
    eeprom_wbit( addr, reg&(1<<i) );
  }

  /* write data MSB first    */
  for(i=15; i>=0; i--) {
    eeprom_wbit( addr, data&(1<<i) );
  }

  /* reset cs  */
  outl(inl(EEREG) & ~(1<<EECS_BIT),EEREG);
}


/*
 * read the specified eeprom register 
 */
int eeprom_rreg(  unsigned int addr, int reg ) {
  int data,i;

  /* set clock low  */
  outl(inl(EEREG) & (~(1<<EECLK_BIT)),EEREG);

  /* set cs  */
  outl(inl(EEREG) | (1<<EECS_BIT),EEREG);

  /* Write Register Command */
  eeprom_wbit( addr, 1 );
  eeprom_wbit( addr, 1 );
  eeprom_wbit( addr, 0 );

  /* write address MSB first */
  for(i=(EEPROM_ALEN-1); i>=0; i--) {
    eeprom_wbit( addr, reg & (1<<i) );
  }

  data = 0;
  /* write data MSB first    */
  for(i=15; i>=0; i--) {
    data |= (eeprom_rbit( addr )<<i);
  }

  /* reset cs  */
  outl(inl(EEREG) & ~(1<<EECS_BIT),EEREG);

  return data;
}


/**
 * @short Writes the data to the EEPROM
 */
void rf_ee_write_data( device_t *dev_rf ) {
  int i,j;

  PR_DBG( 4, "Using address %x\n", dev_rf->addr[1] );
  eeprom_wen( dev_rf->addr[1] );
  for ( j=0; j<10; j++) {
    udelay(19999);
  }

  for ( i=0;i<EEPROM_LENGTH;i++ ) {
    eeprom_wreg( dev_rf->addr[1], i, eedata[i] );
    PR_DBG( 4, "Writing reg %x : %x\n", i, eedata[i] );
    for ( j=0;j<10;j++ ) {
      udelay(19999);
    }
  }
}


/**
 * @short Reads the data in the EEPROM and displays it
 */
void rf_ee_read_data( device_t *dev_rf ) {
  int i;

  PR_DBG( 4, "Using address %x\n", dev_rf->addr[1] );
  for ( i=0; i<EEPROM_LENGTH; i++ ) {
    PR_DBG( 0, "Reg %x : %x\n", i, eeprom_rreg( dev_rf->addr[1], i ) );
  }
}