📄 xs.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity xs is
port(s,clk:in std_logic;
js1,js10a:in std_logic_vector(0 to 3);
r,g,y:out std_logic);
end xs;
architecture stl of xs is
begin
process(clk,s,js1,js10a)
variable red,green,yellow: std_logic :='0';
begin
if( s='0'and conv_integer(js1)<=3 and js10a="0011")then
red:='0';green:=not clk;yellow:='0';
elsif(clk='0' and clk'event)then
if(s='0' and conv_integer(js1)>=3 and js10a="0011" )then
red:='0';green:='0';yellow:='1';
elsif(s='0'and js10a /="0011")then
red:='0';green:='1';yellow:='0';
elsif(s='1')then
red:='1';green:='0';yellow:='0';
end if;
end if;
r<=red;g<=green;y<=yellow;
end process;
end stl;
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