📄 js.rpt
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(38) 20 B SOFT t 0 0 0 0 2 1 0 |LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node1
(28) 28 B SOFT t 0 0 0 0 3 1 0 |LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node2
(29) 27 B SOFT t 0 0 0 0 4 1 0 |LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node3
(32) 25 B SOFT t 0 0 0 0 2 1 0 |LPM_ADD_SUB:197|addcore:adder|addcore:adder0|gcp2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2\jiaotongdeng\js.rpt
js
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------- LC22 led10
| +--------------------- LC24 led10a0
| | +------------------- LC17 led10a1
| | | +----------------- LC19 led10a2
| | | | +--------------- LC21 led10a3
| | | | | +------------- LC18 led11
| | | | | | +----------- LC23 led12
| | | | | | | +--------- LC26 led13
| | | | | | | | +------- LC20 |LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | +----- LC28 |LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | | +--- LC27 |LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | | +- LC25 |LPM_ADD_SUB:197|addcore:adder|addcore:adder0|gcp2
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC22 -> * * * * * * * - - - * - | - * | <-- led10
LC24 -> - * * - - - - - - - - - | - * | <-- led10a0
LC17 -> - * * - - - - - - - - * | - * | <-- led10a1
LC19 -> - * * * - - - - - - - * | - * | <-- led10a2
LC21 -> - * * * * - - - - - - - | - * | <-- led10a3
LC18 -> * * * * * * * - - * * - | - * | <-- led11
LC23 -> * * * * * * * - * * * - | - * | <-- led12
LC26 -> * * * * * * * * * * * - | - * | <-- led13
LC20 -> - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node1
LC28 -> - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node2
LC27 -> * - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node3
LC25 -> - * - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:197|addcore:adder|addcore:adder0|gcp2
Pin
43 -> - - - - - - - - - - - - | - - | <-- clk
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\jiaotongdeng\js.rpt
js
** EQUATIONS **
clk : INPUT;
-- Node name is 'led10' = 'ledd10'
-- Equation name is 'led10', location is LC022, type is output.
led10 = DFFE( _EQ001 $ _LC027, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC027 & !led10 & !led11 & !led12 & !led13;
-- Node name is 'led10a0' = 'ledd100'
-- Equation name is 'led10a0', location is LC024, type is output.
led10a0 = TFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC025 & !led10 & !led10a0 & led10a1 & !led10a3 & !led11 &
!led12 & !led13
# !_LC025 & !led10 & !led10a0 & led10a2 & !led10a3 & !led11 &
!led12 & !led13
# !_LC025 & !led10 & led10a0 & !led10a3 & !led11 & !led12 & !led13;
-- Node name is 'led10a1' = 'ledd101'
-- Equation name is 'led10a1', location is LC017, type is output.
led10a1 = TFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !led10 & led10a0 & !led10a1 & !led10a2 & !led10a3 & !led11 &
!led12 & !led13
# !led10 & led10a1 & !led10a2 & !led10a3 & !led11 & !led12 & !led13;
-- Node name is 'led10a2' = 'ledd102'
-- Equation name is 'led10a2', location is LC019, type is output.
led10a2 = TFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !led10 & !led10a3 & !led11 & !led12 & !led13;
-- Node name is 'led10a3' = 'ledd103'
-- Equation name is 'led10a3', location is LC021, type is output.
led10a3 = TFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !led10 & !led11 & !led12 & !led13;
-- Node name is 'led11' = 'ledd11'
-- Equation name is 'led11', location is LC018, type is output.
led11 = DFFE( _EQ006 $ _LC028, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC028 & !led10 & !led11 & !led12 & !led13;
-- Node name is 'led12' = 'ledd12'
-- Equation name is 'led12', location is LC023, type is output.
led12 = DFFE( _EQ007 $ _LC020, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC020 & !led10 & !led11 & !led12 & !led13;
-- Node name is 'led13' = 'ledd13'
-- Equation name is 'led13', location is LC026, type is output.
led13 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( led12 $ !led13);
-- Node name is '|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( led11 $ _EQ008);
_EQ008 = !led12 & !led13;
-- Node name is '|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( led10 $ _EQ009);
_EQ009 = !led11 & !led12 & !led13;
-- Node name is '|LPM_ADD_SUB:197|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( _EQ010 $ led10a1);
_EQ010 = !led10a1 & led10a2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\maxplus2\jiaotongdeng\js.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,465K
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