📄 js.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity js is
port(clk:in std_logic;
led1,led10a:out std_logic_vector(0 to 3));
end js;
architecture stl of js is
signal ledd1:std_logic_vector(0 to 3) :="1001";
signal ledd10:std_logic_vector(0 to 3) :="0011";
begin
a1:process(clk)
begin
if(clk='1' and clk'event)then
if(ledd1="0000")then
ledd1<="1001";
else ledd1<=ledd1-1;
end if;
end if;
end process a1;
a2:process(clk,ledd1)
begin
if(clk='1' and clk'event)then
if(ledd1="0000")then
if(ledd10="0000")then
ledd10<="0011";
else ledd10<=ledd10-1;
end if;
end if;
end if;
end process a2;
led1<=ledd1;led10a<=ledd10;
end stl;
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