xs1.vhd

来自「基本交通系统,实现城市交通路口的模拟仿真」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity xs1 is
 port(s:in std_logic;
js1,js10a:in std_logic_vector(0 to 3);
r,g,y:out std_logic);
end xs1;

architecture stl of xs1 is

  begin

process(s,js1,js10a)
variable red,green,yellow: std_logic :='0';
begin
 
  if(s='1')then
   red:='1';green:='0';yellow:='0';
    elsif(s='0' and conv_integer(js1)<=4 and js10a="0011")then
    case js1 is
      when"0000"=> red:='0';green:='0';yellow:='0';
      when"0001"=> red:='0';green:='1';yellow:='0';
      when"0010"=> red:='0';green:='0';yellow:='0';
      when"0011"=> red:='0';green:='1';yellow:='0';
      when"0100"=> red:='0';green:='0';yellow:='0'; 
      when others => red:='0';green:='0';yellow:='0';
     end case;
 
  elsif(s='0' and conv_integer(js1)>4 and js10a="0011" )then
   red:='0';green:='0';yellow:='1';
    else red:='0';green:='1';yellow:='0';
  end if;

r<=red;g<=green;y<=yellow;
end process;

end stl;