📄 mainkz.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mainkz is
port(clk:in std_logic;
kzs1,kzs2:out std_logic_vector(0 to 3);
s1,s2:out std_logic );
end mainkz;
architecture rtl of mainkz is
signal k1,k2:std_logic_vector(0 to 3) :="0000";
signal ss1:std_logic;
signal ss2:std_logic;
begin
a1:process(clk)
begin
if(clk='1' and clk'event)then
if(k1="1001")then
k1<="0000";
else k1<=k1+1;
end if;
end if;
end process a1;
a2:process(clk,k1)
begin
if(clk='1' and clk'event)then
if(k1="1001")then
if(k2="0011")then
k2<="0000";
else k2<=k2+1;
end if;
end if;
end if;
end process a2;
a3:process(clk,k1,k2)
begin
if(clk='1' and clk'event)then
if(k1="1001"and k2="0011" )or(ss1='0'and ss2='0')then
ss1<=not ss1;
ss2<=ss1;
end if;
end if;
end process a3;
s1<=ss1;s2<=ss2;
kzs1<=k1;kzs2<=k2;
end rtl;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -