jtdmain.vhd

来自「基本交通系统,实现城市交通路口的模拟仿真」· VHDL 代码 · 共 57 行

+library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity jtdmain is
port(clk:in std_logic;
kjs1,kjs10a:out std_logic_vector(0 to 3);
s1,s2:out std_logic  );
end jtdmain;

architecture stl of jtdmain is
signal js1,js10:std_logic_vector(0 to 3) :="0000";
signal ss1:std_logic;
signal ss2:std_logic;

begin 

a1:process(clk)
begin
if(clk='1' and clk'event)then 
 if(js1="1001")then
   js1<="0000";
 else js1<=js1+1;
 end if;
end if;
 end process a1;

a2:process(clk,js1)
begin
if(clk='1' and clk'event)then 
 if(js1="1001")then
 if(js10="0011")then
    js10<="0000";
 else js10<=js10+1;
 end if;
 end if;
end if;
end process a2;

a3:process(clk,js1,js10)
begin
if(clk='1' and clk'event)then 
 if(js1="1001"and js10="0011" )or(ss1='0'and ss2='0')then
   ss1<=not ss1;
   ss2<=ss1;
 end if;
end if;
end process a3;
s1<=ss1;s2<=ss2;
kjs1<=js1;kjs10a<=js10;
end stl;