📄 main.rpt
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-- Node name is 'ledb10b1' = '|js:u5|ledd101'
-- Equation name is 'ledb10b1', type is output
ledb10b1 = TFFE( _EQ016, clk1, VCC, VCC, VCC);
_EQ016 = !ledb10 & ledb10b0 & !ledb10b1 & !ledb10b2 & !ledb10b3 & !ledb11 &
!ledb12 & !ledb13
# !ledb10 & ledb10b1 & !ledb10b2 & !ledb10b3 & !ledb11 & !ledb12 &
!ledb13;
-- Node name is 'ledb10b2' = '|js:u5|ledd102'
-- Equation name is 'ledb10b2', type is output
ledb10b2 = TFFE( _EQ017, clk1, VCC, VCC, VCC);
_EQ017 = !ledb10 & !ledb10b3 & !ledb11 & !ledb12 & !ledb13;
-- Node name is 'ledb10b3' = '|js:u5|ledd103'
-- Equation name is 'ledb10b3', type is output
ledb10b3 = TFFE( _EQ018, clk1, VCC, VCC, VCC);
_EQ018 = !ledb10 & !ledb11 & !ledb12 & !ledb13;
-- Node name is 'ledb11' = '|js:u5|ledd11'
-- Equation name is 'ledb11', type is output
ledb11 = DFFE( _EQ019 $ _LC032, clk1, VCC, VCC, VCC);
_EQ019 = _LC032 & !ledb10 & !ledb11 & !ledb12 & !ledb13;
-- Node name is 'ledb12' = '|js:u5|ledd12'
-- Equation name is 'ledb12', type is output
ledb12 = DFFE( _EQ020 $ _LC031, clk1, VCC, VCC, VCC);
_EQ020 = _LC031 & !ledb10 & !ledb11 & !ledb12 & !ledb13;
-- Node name is 'ledb13' = '|js:u5|ledd13'
-- Equation name is 'ledb13', type is output
ledb13 = TFFE( VCC, clk1, VCC, VCC, VCC);
-- Node name is 'red1' = '|xs:u2|red'
-- Equation name is 'red1', type is output
red1 = DFFE( _EQ021 $ _LC039, !clk1, !_EQ022, VCC, VCC);
_EQ021 = !_LC034 & !_LC039 & !_LC042 & _LC043 & !_LC044 & !_LC045 &
!_LC058 & _LC059 & red1
# !_LC034 & !_LC039 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059 & !_LC060 & red1;
_EQ022 = !_LC034 & !_LC039 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059;
-- Node name is 'red2' = '|xs:u3|red'
-- Equation name is 'red2', type is output
red2 = DFFE( _EQ023 $ _LC038, !clk1, !_EQ024, VCC, VCC);
_EQ023 = !_LC034 & !_LC038 & !_LC042 & _LC043 & !_LC044 & !_LC045 &
!_LC058 & _LC059 & red2
# !_LC034 & !_LC038 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059 & !_LC060 & red2;
_EQ024 = !_LC034 & !_LC038 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059;
-- Node name is 'yellow1' = '|xs:u2|yellow'
-- Equation name is 'yellow1', type is output
yellow1 = DFFE( _EQ025 $ _EQ026, !clk1, !_EQ027, VCC, VCC);
_EQ025 = !_LC034 & !_LC039 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059 & !_LC060 & !yellow1
# !_LC034 & !_LC039 & !_LC042 & _LC043 & !_LC044 & !_LC045 &
!_LC058 & _LC059 & !yellow1;
_EQ026 = !_LC039 & _LC043 & !_LC044 & !_LC045 & _LC059;
_EQ027 = !_LC034 & !_LC039 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059;
-- Node name is 'yellow2' = '|xs:u3|yellow'
-- Equation name is 'yellow2', type is output
yellow2 = DFFE( _EQ028 $ _EQ029, !clk1, !_EQ030, VCC, VCC);
_EQ028 = !_LC034 & !_LC038 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059 & !_LC060 & !yellow2
# !_LC034 & !_LC038 & !_LC042 & _LC043 & !_LC044 & !_LC045 &
!_LC058 & _LC059 & !yellow2;
_EQ029 = !_LC038 & _LC043 & !_LC044 & !_LC045 & _LC059;
_EQ030 = !_LC034 & !_LC038 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059;
-- Node name is '|js:u4|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC050', type is buried
_LC050 = LCELL( leda12 $ !leda13);
-- Node name is '|js:u4|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC054', type is buried
_LC054 = LCELL( leda11 $ _EQ031);
_EQ031 = !leda12 & !leda13;
-- Node name is '|js:u4|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC055', type is buried
_LC055 = LCELL( leda10 $ _EQ032);
_EQ032 = !leda11 & !leda12 & !leda13;
-- Node name is '|js:u4|LPM_ADD_SUB:197|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC056', type is buried
_LC056 = LCELL( _EQ033 $ leda10a1);
_EQ033 = !leda10a1 & leda10a2;
-- Node name is '|js:u5|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( ledb12 $ !ledb13);
-- Node name is '|js:u5|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( ledb11 $ _EQ034);
_EQ034 = !ledb12 & !ledb13;
-- Node name is '|js:u5|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC018', type is buried
_LC018 = LCELL( ledb10 $ _EQ035);
_EQ035 = !ledb11 & !ledb12 & !ledb13;
-- Node name is '|js:u5|LPM_ADD_SUB:197|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( _EQ036 $ ledb10b1);
_EQ036 = !ledb10b1 & ledb10b2;
-- Node name is '|jtdmain:u1|:12' = '|jtdmain:u1|js10'
-- Equation name is '_LC034', type is buried
_LC034 = DFFE( _EQ037 $ _LC061, clk1, VCC, VCC, VCC);
_EQ037 = _LC034 & !_LC042 & !_LC058 & _LC060 & _LC061;
-- Node name is '|jtdmain:u1|:13' = '|jtdmain:u1|js11'
-- Equation name is '_LC058', type is buried
_LC058 = TFFE( _EQ038, clk1, VCC, VCC, VCC);
_EQ038 = _LC042 & _LC060;
-- Node name is '|jtdmain:u1|:14' = '|jtdmain:u1|js12'
-- Equation name is '_LC042', type is buried
_LC042 = DFFE( _EQ039 $ _LC063, clk1, VCC, VCC, VCC);
_EQ039 = _LC034 & !_LC042 & !_LC058 & _LC060 & _LC063;
-- Node name is '|jtdmain:u1|:15' = '|jtdmain:u1|js13'
-- Equation name is '_LC060', type is buried
_LC060 = TFFE( VCC, clk1, VCC, VCC, VCC);
-- Node name is '|jtdmain:u1|:16' = '|jtdmain:u1|js100'
-- Equation name is '_LC045', type is buried
_LC045 = TFFE( _EQ040, clk1, VCC, VCC, VCC);
_EQ040 = _LC034 & !_LC042 & _LC043 & _LC044 & !_LC058 & _LC059 &
_LC060;
-- Node name is '|jtdmain:u1|:17' = '|jtdmain:u1|js101'
-- Equation name is '_LC044', type is buried
_LC044 = TFFE( _EQ041, clk1, VCC, VCC, VCC);
_EQ041 = _LC034 & !_LC042 & _LC043 & !_LC044 & _LC045 & !_LC058 &
_LC059 & _LC060
# _LC034 & !_LC042 & _LC043 & _LC044 & !_LC058 & _LC059 &
_LC060;
-- Node name is '|jtdmain:u1|:18' = '|jtdmain:u1|js102'
-- Equation name is '_LC043', type is buried
_LC043 = TFFE( _EQ042, clk1, VCC, VCC, VCC);
_EQ042 = _LC034 & !_LC042 & !_LC058 & _LC059 & _LC060;
-- Node name is '|jtdmain:u1|:19' = '|jtdmain:u1|js103'
-- Equation name is '_LC059', type is buried
_LC059 = TFFE( _EQ043, clk1, VCC, VCC, VCC);
_EQ043 = _LC034 & !_LC042 & !_LC058 & _LC060;
-- Node name is '|jtdmain:u1|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC063', type is buried
_LC063 = LCELL( _LC042 $ _LC060);
-- Node name is '|jtdmain:u1|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC061', type is buried
_LC061 = LCELL( _LC034 $ _EQ044);
_EQ044 = _LC042 & _LC058 & _LC060;
-- Node name is '|jtdmain:u1|:20' = '|jtdmain:u1|ss1'
-- Equation name is '_LC039', type is buried
_LC039 = TFFE( _EQ045, clk1, VCC, VCC, VCC);
_EQ045 = _LC034 & !_LC042 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059 & _LC060
# !_LC038 & !_LC039;
-- Node name is '|jtdmain:u1|:21' = '|jtdmain:u1|ss2'
-- Equation name is '_LC038', type is buried
_LC038 = TFFE( _EQ046, clk1, VCC, VCC, VCC);
_EQ046 = _LC034 & !_LC038 & _LC039 & !_LC042 & _LC043 & !_LC044 &
!_LC045 & !_LC058 & _LC059 & _LC060
# _LC034 & _LC038 & !_LC039 & !_LC042 & _LC043 & !_LC044 &
!_LC045 & !_LC058 & _LC059 & _LC060;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\maxplus2\jiaotongdeng\main.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = off
Automatic Global Clear = off
Automatic Global Preset = off
Automatic Global Output Enable = off
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,030K
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