📄 main.rpt
字号:
- 44 C TFFE t 0 0 0 1 8 6 4 |jtdmain:u1|js101 (|jtdmain:u1|:17)
- 43 C TFFE t 0 0 0 1 5 6 4 |jtdmain:u1|js102 (|jtdmain:u1|:18)
- 59 D TFFE t 0 0 0 1 4 6 5 |jtdmain:u1|js103 (|jtdmain:u1|:19)
- 39 C TFFE t 0 0 0 1 10 3 2 |jtdmain:u1|ss1 (|jtdmain:u1|:20)
- 38 C TFFE t 0 0 0 1 10 3 2 |jtdmain:u1|ss2 (|jtdmain:u1|:21)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2\jiaotongdeng\main.rpt
main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC4 leda13
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B C D | Logic cells that feed LAB 'A':
Pin
12 -> * | * * * * | <-- clk1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\jiaotongdeng\main.rpt
main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------- LC31 |js:u5|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node1
| +------------------- LC32 |js:u5|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node2
| | +----------------- LC18 |js:u5|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node3
| | | +--------------- LC27 |js:u5|LPM_ADD_SUB:197|addcore:adder|addcore:adder0|gcp2
| | | | +------------- LC30 ledb10
| | | | | +----------- LC25 ledb10b0
| | | | | | +--------- LC24 ledb10b1
| | | | | | | +------- LC19 ledb10b2
| | | | | | | | +----- LC17 ledb10b3
| | | | | | | | | +--- LC21 ledb11
| | | | | | | | | | +- LC20 ledb12
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC31 -> - - - - - - - - - - * | - * - - | <-- |js:u5|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node1
LC32 -> - - - - - - - - - * - | - * - - | <-- |js:u5|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node2
LC18 -> - - - - * - - - - - - | - * - - | <-- |js:u5|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node3
LC27 -> - - - - - * - - - - - | - * - - | <-- |js:u5|LPM_ADD_SUB:197|addcore:adder|addcore:adder0|gcp2
LC30 -> - - * - * * * * * * * | - * - - | <-- ledb10
LC25 -> - - - - - * * - - - - | - * - - | <-- ledb10b0
LC24 -> - - - * - * * - - - - | - * - - | <-- ledb10b1
LC19 -> - - - * - * * * - - - | - * - - | <-- ledb10b2
LC17 -> - - - - - * * * * - - | - * - - | <-- ledb10b3
LC21 -> - * * - * * * * * * * | - * - - | <-- ledb11
LC20 -> * * * - * * * * * * * | - * - - | <-- ledb12
Pin
12 -> - - - - * * * * * * * | * * * * | <-- clk1
LC33 -> * * * - * * * * * * * | - * - - | <-- ledb13
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\jiaotongdeng\main.rpt
main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------------------- LC46 green1
| +------------------------- LC37 green2
| | +----------------------- LC34 |jtdmain:u1|js10
| | | +--------------------- LC42 |jtdmain:u1|js12
| | | | +------------------- LC45 |jtdmain:u1|js100
| | | | | +----------------- LC44 |jtdmain:u1|js101
| | | | | | +--------------- LC43 |jtdmain:u1|js102
| | | | | | | +------------- LC39 |jtdmain:u1|ss1
| | | | | | | | +----------- LC38 |jtdmain:u1|ss2
| | | | | | | | | +--------- LC33 ledb13
| | | | | | | | | | +------- LC35 red1
| | | | | | | | | | | +----- LC36 red2
| | | | | | | | | | | | +--- LC40 yellow1
| | | | | | | | | | | | | +- LC41 yellow2
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC46 -> * - - - - - - - - - - - - - | - - * - | <-- green1
LC37 -> - * - - - - - - - - - - - - | - - * - | <-- green2
LC34 -> * * * * * * * * * - * * * * | - - * * | <-- |jtdmain:u1|js10
LC42 -> * * * * * * * * * - * * * * | - - * * | <-- |jtdmain:u1|js12
LC45 -> * * - - * * - * * - * * * * | - - * - | <-- |jtdmain:u1|js100
LC44 -> * * - - * * - * * - * * * * | - - * - | <-- |jtdmain:u1|js101
LC43 -> * * - - * * * * * - * * * * | - - * - | <-- |jtdmain:u1|js102
LC39 -> * - - - - - - * * - * - * - | - - * - | <-- |jtdmain:u1|ss1
LC38 -> - * - - - - - * * - - * - * | - - * - | <-- |jtdmain:u1|ss2
LC35 -> - - - - - - - - - - * - - - | - - * - | <-- red1
LC36 -> - - - - - - - - - - - * - - | - - * - | <-- red2
LC40 -> - - - - - - - - - - - - * - | - - * - | <-- yellow1
LC41 -> - - - - - - - - - - - - - * | - - * - | <-- yellow2
Pin
12 -> * * * * * * * * * * * * * * | * * * * | <-- clk1
LC63 -> - - - * - - - - - - - - - - | - - * - | <-- |jtdmain:u1|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1
LC61 -> - - * - - - - - - - - - - - | - - * - | <-- |jtdmain:u1|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3
LC58 -> * * * * * * * * * - * * * * | - - * * | <-- |jtdmain:u1|js11
LC60 -> * * * * * * * * * - * * * * | - - * * | <-- |jtdmain:u1|js13
LC59 -> * * - - * * * * * - * * * * | - - * - | <-- |jtdmain:u1|js103
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\jiaotongdeng\main.rpt
main
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC50 |js:u4|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node1
| +----------------------------- LC54 |js:u4|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node2
| | +--------------------------- LC55 |js:u4|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node3
| | | +------------------------- LC56 |js:u4|LPM_ADD_SUB:197|addcore:adder|addcore:adder0|gcp2
| | | | +----------------------- LC63 |jtdmain:u1|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1
| | | | | +--------------------- LC61 |jtdmain:u1|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3
| | | | | | +------------------- LC58 |jtdmain:u1|js11
| | | | | | | +----------------- LC60 |jtdmain:u1|js13
| | | | | | | | +--------------- LC59 |jtdmain:u1|js103
| | | | | | | | | +------------- LC51 leda10
| | | | | | | | | | +----------- LC53 leda10a0
| | | | | | | | | | | +--------- LC57 leda10a1
| | | | | | | | | | | | +------- LC49 leda10a2
| | | | | | | | | | | | | +----- LC52 leda10a3
| | | | | | | | | | | | | | +--- LC64 leda11
| | | | | | | | | | | | | | | +- LC62 leda12
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC50 -> - - - - - - - - - - - - - - - * | - - - * | <-- |js:u4|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node1
LC54 -> - - - - - - - - - - - - - - * - | - - - * | <-- |js:u4|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node2
LC55 -> - - - - - - - - - * - - - - - - | - - - * | <-- |js:u4|LPM_ADD_SUB:60|addcore:adder|addcore:adder0|result_node3
LC56 -> - - - - - - - - - - * - - - - - | - - - * | <-- |js:u4|LPM_ADD_SUB:197|addcore:adder|addcore:adder0|gcp2
LC58 -> - - - - - * * - * - - - - - - - | - - * * | <-- |jtdmain:u1|js11
LC60 -> - - - - * * * * * - - - - - - - | - - * * | <-- |jtdmain:u1|js13
LC51 -> - - * - - - - - - * * * * * * * | - - - * | <-- leda10
LC53 -> - - - - - - - - - - * * - - - - | - - - * | <-- leda10a0
LC57 -> - - - * - - - - - - * * - - - - | - - - * | <-- leda10a1
LC49 -> - - - * - - - - - - * * * - - - | - - - * | <-- leda10a2
LC52 -> - - - - - - - - - - * * * * - - | - - - * | <-- leda10a3
LC64 -> - * * - - - - - - * * * * * * * | - - - * | <-- leda11
LC62 -> * * * - - - - - - * * * * * * * | - - - * | <-- leda12
Pin
12 -> - - - - - - * * * * * * * * * * | * * * * | <-- clk1
LC34 -> - - - - - * - - * - - - - - - - | - - * * | <-- |jtdmain:u1|js10
LC42 -> - - - - * * * - * - - - - - - - | - - * * | <-- |jtdmain:u1|js12
LC4 -> * * * - - - - - - * * * * * * * | - - - * | <-- leda13
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\jiaotongdeng\main.rpt
main
** EQUATIONS **
clk1 : INPUT;
-- Node name is 'green1' = '|xs:u2|green'
-- Equation name is 'green1', type is output
green1 = DFFE( _EQ001 $ GND, !clk1, !_EQ002, !_EQ003, VCC);
_EQ001 = green1 & !_LC034 & !_LC039 & !_LC058 & _X001
# !_LC039 & _X002;
_X001 = EXP( _LC042 & _LC060);
_X002 = EXP( _LC043 & !_LC044 & !_LC045 & _LC059);
_EQ002 = clk1 & !_LC034 & !_LC039 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059;
_EQ003 = !clk1 & !_LC034 & !_LC039 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059;
-- Node name is 'green2' = '|xs:u3|green'
-- Equation name is 'green2', type is output
green2 = DFFE( _EQ004 $ GND, !clk1, !_EQ005, !_EQ006, VCC);
_EQ004 = green2 & !_LC034 & !_LC038 & !_LC058 & _X001
# !_LC038 & _X002;
_X001 = EXP( _LC042 & _LC060);
_X002 = EXP( _LC043 & !_LC044 & !_LC045 & _LC059);
_EQ005 = clk1 & !_LC034 & !_LC038 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059;
_EQ006 = !clk1 & !_LC034 & !_LC038 & _LC043 & !_LC044 & !_LC045 & !_LC058 &
_LC059;
-- Node name is 'leda10' = '|js:u4|ledd10'
-- Equation name is 'leda10', type is output
leda10 = DFFE( _EQ007 $ _LC055, clk1, VCC, VCC, VCC);
_EQ007 = !_LC055 & !leda10 & !leda11 & !leda12 & !leda13;
-- Node name is 'leda10a0' = '|js:u4|ledd100'
-- Equation name is 'leda10a0', type is output
leda10a0 = TFFE( _EQ008, clk1, VCC, VCC, VCC);
_EQ008 = !_LC056 & !leda10 & !leda10a0 & leda10a1 & !leda10a3 & !leda11 &
!leda12 & !leda13
# !_LC056 & !leda10 & !leda10a0 & leda10a2 & !leda10a3 & !leda11 &
!leda12 & !leda13
# !_LC056 & !leda10 & leda10a0 & !leda10a3 & !leda11 & !leda12 &
!leda13;
-- Node name is 'leda10a1' = '|js:u4|ledd101'
-- Equation name is 'leda10a1', type is output
leda10a1 = TFFE( _EQ009, clk1, VCC, VCC, VCC);
_EQ009 = !leda10 & leda10a0 & !leda10a1 & !leda10a2 & !leda10a3 & !leda11 &
!leda12 & !leda13
# !leda10 & leda10a1 & !leda10a2 & !leda10a3 & !leda11 & !leda12 &
!leda13;
-- Node name is 'leda10a2' = '|js:u4|ledd102'
-- Equation name is 'leda10a2', type is output
leda10a2 = TFFE( _EQ010, clk1, VCC, VCC, VCC);
_EQ010 = !leda10 & !leda10a3 & !leda11 & !leda12 & !leda13;
-- Node name is 'leda10a3' = '|js:u4|ledd103'
-- Equation name is 'leda10a3', type is output
leda10a3 = TFFE( _EQ011, clk1, VCC, VCC, VCC);
_EQ011 = !leda10 & !leda11 & !leda12 & !leda13;
-- Node name is 'leda11' = '|js:u4|ledd11'
-- Equation name is 'leda11', type is output
leda11 = DFFE( _EQ012 $ _LC054, clk1, VCC, VCC, VCC);
_EQ012 = _LC054 & !leda10 & !leda11 & !leda12 & !leda13;
-- Node name is 'leda12' = '|js:u4|ledd12'
-- Equation name is 'leda12', type is output
leda12 = DFFE( _EQ013 $ _LC050, clk1, VCC, VCC, VCC);
_EQ013 = _LC050 & !leda10 & !leda11 & !leda12 & !leda13;
-- Node name is 'leda13' = '|js:u4|ledd13'
-- Equation name is 'leda13', type is output
leda13 = TFFE( VCC, clk1, VCC, VCC, VCC);
-- Node name is 'ledb10' = '|js:u5|ledd10'
-- Equation name is 'ledb10', type is output
ledb10 = DFFE( _EQ014 $ _LC018, clk1, VCC, VCC, VCC);
_EQ014 = !_LC018 & !ledb10 & !ledb11 & !ledb12 & !ledb13;
-- Node name is 'ledb10b0' = '|js:u5|ledd100'
-- Equation name is 'ledb10b0', type is output
ledb10b0 = TFFE( _EQ015, clk1, VCC, VCC, VCC);
_EQ015 = !_LC027 & !ledb10 & !ledb10b0 & ledb10b1 & !ledb10b3 & !ledb11 &
!ledb12 & !ledb13
# !_LC027 & !ledb10 & !ledb10b0 & ledb10b2 & !ledb10b3 & !ledb11 &
!ledb12 & !ledb13
# !_LC027 & !ledb10 & ledb10b0 & !ledb10b3 & !ledb11 & !ledb12 &
!ledb13;
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