mainkz.rpt

基本交通系统,实现城市交通路口的模拟仿真

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (32)    25    B       SOFT      t        0      0   0    0    2    1    0  |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1
 (38)    20    B       SOFT      t        0      0   0    0    4    1    0  |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:           d:\vhdl shi xun\jiaotongdeng\mainkz.rpt
mainkz

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                 Logic cells placed in LAB 'B'
        +----------------------- LC23 kzs10
        | +--------------------- LC24 kzs11
        | | +------------------- LC17 kzs12
        | | | +----------------- LC18 kzs13
        | | | | +--------------- LC21 kzs20
        | | | | | +------------- LC19 kzs21
        | | | | | | +----------- LC22 kzs22
        | | | | | | | +--------- LC27 kzs23
        | | | | | | | | +------- LC25 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1
        | | | | | | | | | +----- LC20 |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3
        | | | | | | | | | | +--- LC28 s1
        | | | | | | | | | | | +- LC26 s2
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC23 -> * - * - * * * * - * * * | - * | <-- kzs10
LC24 -> * * * - * * * * - * * * | - * | <-- kzs11
LC17 -> * * * - * * * * * * * * | - * | <-- kzs12
LC18 -> * * * * * * * * * * * * | - * | <-- kzs13
LC21 -> - - - - * * - - - - * * | - * | <-- kzs20
LC19 -> - - - - * * - - - - * * | - * | <-- kzs21
LC22 -> - - - - * * * - - - * * | - * | <-- kzs22
LC27 -> - - - - * * * * - - * * | - * | <-- kzs23
LC25 -> - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1
LC20 -> * - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3
LC28 -> - - - - - - - - - - * * | - * | <-- s1
LC26 -> - - - - - - - - - - * * | - * | <-- s2

Pin
43   -> - - - - - - - - - - - - | - - | <-- clk


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           d:\vhdl shi xun\jiaotongdeng\mainkz.rpt
mainkz

** EQUATIONS **

clk      : INPUT;

-- Node name is 'kzs10' = 'k10' 
-- Equation name is 'kzs10', location is LC023, type is output.
 kzs10   = DFFE( _EQ001 $  _LC020, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  kzs10 & !kzs11 & !kzs12 &  kzs13 &  _LC020;

-- Node name is 'kzs11' = 'k11' 
-- Equation name is 'kzs11', location is LC024, type is output.
 kzs11   = TFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  kzs12 &  kzs13;

-- Node name is 'kzs12' = 'k12' 
-- Equation name is 'kzs12', location is LC017, type is output.
 kzs12   = DFFE( _EQ003 $  _LC025, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  kzs10 & !kzs11 & !kzs12 &  kzs13 &  _LC025;

-- Node name is 'kzs13' = 'k13' 
-- Equation name is 'kzs13', location is LC018, type is output.
 kzs13   = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is 'kzs20' = 'k20' 
-- Equation name is 'kzs20', location is LC021, type is output.
 kzs20   = TFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  kzs10 & !kzs11 & !kzs12 &  kzs13 &  kzs21 &  kzs22 &  kzs23;

-- Node name is 'kzs21' = 'k21' 
-- Equation name is 'kzs21', location is LC019, type is output.
 kzs21   = TFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  kzs10 & !kzs11 & !kzs12 &  kzs13 &  kzs20 & !kzs21 &  kzs22 & 
              kzs23
         #  kzs10 & !kzs11 & !kzs12 &  kzs13 &  kzs21 &  kzs22 &  kzs23;

-- Node name is 'kzs22' = 'k22' 
-- Equation name is 'kzs22', location is LC022, type is output.
 kzs22   = TFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  kzs10 & !kzs11 & !kzs12 &  kzs13 &  kzs23;

-- Node name is 'kzs23' = 'k23' 
-- Equation name is 'kzs23', location is LC027, type is output.
 kzs23   = TFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  kzs10 & !kzs11 & !kzs12 &  kzs13;

-- Node name is 's1' = 'ss1' 
-- Equation name is 's1', location is LC028, type is output.
 s1      = TFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  kzs10 & !kzs11 & !kzs12 &  kzs13 & !kzs20 & !kzs21 &  kzs22 & 
              kzs23
         # !s1 & !s2;

-- Node name is 's2' = 'ss2' 
-- Equation name is 's2', location is LC026, type is output.
 s2      = TFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  kzs10 & !kzs11 & !kzs12 &  kzs13 & !kzs20 & !kzs21 &  kzs22 & 
              kzs23 &  s1 & !s2
         #  kzs10 & !kzs11 & !kzs12 &  kzs13 & !kzs20 & !kzs21 &  kzs22 & 
              kzs23 & !s1 &  s2;

-- Node name is '|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( kzs12 $  kzs13);

-- Node name is '|LPM_ADD_SUB:64|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( kzs10 $  _EQ010);
  _EQ010 =  kzs11 &  kzs12 &  kzs13;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                    d:\vhdl shi xun\jiaotongdeng\mainkz.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,450K