disp.vhd

来自「这是一个数字中的课程设计」· VHDL 代码 · 共 29 行

LIBRARY ieee;
use ieee.std_logic_1164.all;
ENTITY disp IS
	PORT(
		   d			: IN	STD_LOGIC_VECTOR(3 downto 0);
		   q	        : OUT	STD_LOGIC_vector(6 downto 0));
END disp;
ARCHITECTURE disp_arc OF disp IS
BEGIN
  Process (d)
  begin
    case d is
      when"0000"=>q<="0111111";
      when"0001"=>q<="0000110";
      when"0010"=>q<="1011011";
      when"0011"=>q<="1001111";
      when"0100"=>q<="1100110";
      when"0101"=>q<="1101101";
      when"0110"=>q<="1111101";
      when"0111"=>q<="0100111";
      when"1000"=>q<="1111111";
      when"1001"=>q<="1101111";
      when others=>q<="0000000";
    end case;
  end process;
END disp_arc;