alarm.vhd

来自「这是一个数字中的课程设计」· VHDL 代码 · 共 27 行

LIBRARY ieee;
use ieee.std_logic_1164.all;
ENTITY alarm IS
   PORT(amin1,amin0,ah1,ah0,min1,min0,h1,h0   :in  std_logic_vector(3 downto 0);
        mode   	                              :IN  STD_LOGIC;
		a1,a0,b1,b0                           :OUT std_logic_vector(3 downto 0));
END alarm;
ARCHITECTURE art OF alarm IS
BEGIN
  Process (mode,min1,min0,h1,h0,amin1,amin0,ah1,ah0)
begin
            if mode='0'then
               a1<=min1;
                 a0<=min0;
                    b1<=h1;
                      b0<=h0;
           else      
              a1<=amin1;
           a0<=amin0;
         b1<=ah1;
       b0<=ah0;
            
 end if; 
end process;
end art;