xsxz.vhd

来自「这是一个数字中的课程设计」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
entity xsxz is
port(sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);
sel:in std_logic_vector(2 downto 0);
q:out std_logic_vector(3 downto 0));
end xsxz;
architecture art of xsxz is
begin
process(sel)
begin
			case sel is
			when "000"=>q<=h1;
			when "001"=>q<=h0;
			when "011"=>q<=min1;
			when "100"=>q<=min0;
			when "110"=>q<=sec1;
			when "111"=>q<=sec0;
			when others=>q<="1111";
			end case;
		end process;
end art;