ncca-m-01.c

基于单片机AT89c51ed2的CAN通讯

#include "AT89S8252.H"
#include "absacc.h"

#define FIFO_LEVEL 16
#define UBYTE unsigned char

#define SJA_REG_BaseADD 0x0800	 

#define RAM_DATA_IN_BASE  0x000
#define RAM_DATA_OUT_BASE 0x200
#define RAM_PARA_IN_BASE  0x400
#define RAM_PARA_OUT_BASE 0x520
#define RAM_CTRL_AREA_BASE 0x7C0
#define NODEID_ADDR 0x640
#define IN_IO_LENGTH 0x7F0
#define OUT_IO_LENGTH 0x7F6
#define BusStatusAddr 0x7DA 

#define REG_MOD     XBYTE[SJA_REG_BaseADD + 0x00]//0
#define REG_CMD     XBYTE[SJA_REG_BaseADD + 0x01]//1
#define REG_SR      XBYTE[SJA_REG_BaseADD + 0x02]//2
#define REG_IFR     XBYTE[SJA_REG_BaseADD + 0x03]//3
#define REG_IER     XBYTE[SJA_REG_BaseADD + 0x04]//4
#define REG_BTR0    XBYTE[SJA_REG_BaseADD + 0x06]//6  05 rvd
#define REG_BTR1    XBYTE[SJA_REG_BaseADD + 0x07]//7
#define REG_OCR     XBYTE[SJA_REG_BaseADD + 0x08]//8
#define REG_TEST    XBYTE[SJA_REG_BaseADD + 0x09]//9
#define REG_ALC     XBYTE[SJA_REG_BaseADD + 0x0b]//11 0a rvd
#define REG_ECC     XBYTE[SJA_REG_BaseADD + 0x0c]//12
#define REG_EWLR    XBYTE[SJA_REG_BaseADD + 0x0d]//13
#define REG_RXERR   XBYTE[SJA_REG_BaseADD + 0x0e]//14
#define REG_TXERR   XBYTE[SJA_REG_BaseADD + 0x0f]//15

#define REG_ACR0 XBYTE[SJA_REG_BaseADD + 0x10]//16
#define REG_ACR1 XBYTE[SJA_REG_BaseADD + 0x11]//17
#define REG_ACR2 XBYTE[SJA_REG_BaseADD + 0x12]//18
#define REG_ACR3 XBYTE[SJA_REG_BaseADD + 0x13]//19
#define REG_AMR0 XBYTE[SJA_REG_BaseADD + 0x14]//20
#define REG_AMR1 XBYTE[SJA_REG_BaseADD + 0x15]//21
#define REG_AMR2 XBYTE[SJA_REG_BaseADD + 0x16]//22
#define REG_AMR3 XBYTE[SJA_REG_BaseADD + 0x17]//23

#define REG_RxIDBuffer0 XBYTE[SJA_REG_BaseADD + 0x10]//16
#define REG_RxIDBuffer1 XBYTE[SJA_REG_BaseADD + 0x11]//17
#define REG_RxIDBuffer2 XBYTE[SJA_REG_BaseADD + 0x12]//18
#define REG_RxIDBuffer3 XBYTE[SJA_REG_BaseADD + 0x13]//19
#define REG_RxIDBuffer4 XBYTE[SJA_REG_BaseADD + 0x14]//20
//
#define REG_TxIDBuffer0 XBYTE[SJA_REG_BaseADD + 0x10]//16
#define REG_TxIDBuffer1 XBYTE[SJA_REG_BaseADD + 0x11]//17
#define REG_TxIDBuffer2 XBYTE[SJA_REG_BaseADD + 0x12]//18
#define REG_TxIDBuffer3 XBYTE[SJA_REG_BaseADD + 0x13]//19
#define REG_TxIDBuffer4 XBYTE[SJA_REG_BaseADD + 0x14]//20

#define REG_DataBuffer1 XBYTE[SJA_REG_BaseADD + 0x15]//21
#define REG_DataBuffer2 XBYTE[SJA_REG_BaseADD + 0x16]//22
#define REG_DataBuffer3 XBYTE[SJA_REG_BaseADD + 0x17]//23
#define REG_DataBuffer4 XBYTE[SJA_REG_BaseADD + 0x18]//24
#define REG_DataBuffer5 XBYTE[SJA_REG_BaseADD + 0x19]//25
#define REG_DataBuffer6 XBYTE[SJA_REG_BaseADD + 0x1a]//26
#define REG_DataBuffer7 XBYTE[SJA_REG_BaseADD + 0x1b]//27
#define REG_DataBuffer8 XBYTE[SJA_REG_BaseADD + 0x1c]//28
//
#define REG_RMC   XBYTE[SJA_REG_BaseADD + 0x1d]//29
#define REG_RBSA  XBYTE[SJA_REG_BaseADD + 0x1e]//30
#define REG_CDR   XBYTE[SJA_REG_BaseADD + 0x1f]//31

unsigned char xdata _REG_CMD   _at_ 0x801;
unsigned char xdata _REG_SR    _at_ 0x802;
unsigned char xdata _REG_ACR0  _at_ 0x810;
unsigned char xdata _REG_ACR1  _at_ 0x811;
unsigned char xdata _REG_ACR2  _at_ 0x812;
unsigned char xdata _REG_ACR3  _at_ 0x813;
unsigned char xdata _REG_AMR0  _at_ 0x814;
unsigned char xdata _REG_AMR1  _at_ 0x815;
unsigned char xdata _REG_AMR2  _at_ 0x816;
unsigned char xdata _REG_AMR3  _at_ 0x817;

unsigned char xdata _REG_DataBuffer4  _at_ 0x818;
unsigned char xdata _REG_DataBuffer5  _at_ 0x819;
unsigned char xdata _REG_DataBuffer6  _at_ 0x81a;			
unsigned char xdata _REG_DataBuffer7  _at_ 0x81b;
unsigned char xdata _REG_DataBuffer8  _at_ 0x81c;

#define ON 0
#define OFF 1

sbit SJARst = P1 ^ 1; //SJA1000 reset	
sbit CANComIndicator=P3 ^ 3;   
sbit SPIComIndicator=P1 ^ 3;
sbit ACKM=P1^2;
sbit ACKS=P1^0;
sbit SS=P1^4;
sbit stne=P1^1;

void SPIComm();

struct COBIDD
{
  unsigned int rvd1		  :3;
  unsigned int nodeID   :7;
  unsigned int FuncCode :4;
  unsigned int rvd2	    :2;
  unsigned int rvd3       ;	  
};

struct sja1000TxIDALL
{
  unsigned char TxID3;
  unsigned char TxID4;
  unsigned char TxID1;
  unsigned char TxID2;
};
union canTxIDD
{
  struct COBIDD COBID;
  struct sja1000TxIDALL all; 
};
union canTxIDD 	canTxID;

struct sja1000RxIDALL
{
  unsigned char RxID3;
  unsigned char RxID4;
  unsigned char RxID1;
  unsigned char RxID2;
};
union canRxIDD
{
  struct COBIDD COBID;
  struct sja1000RxIDALL all; 
};
union canRxIDD 	canRxID;  
unsigned char temp_data1,SRcpy,CANOfflinTime,CANRdata[8],CANSdata[8];
UBYTE i;
UBYTE rdata1[17],sdata[16],Sum,SPIOfflinTime;

main()
{
SPIComIndicator=1;
for(i=0;i<16;i++)
{
    sdata[i] = 0;
    rdata1[i] = 0;
}
SPCON=0XFE;
ACKM=ACKS;
 SS=0;
 CANOfflinTime = 0;
 canTxID.all.TxID1=0;
 canTxID.all.TxID2=0;
 canTxID.all.TxID3=0;
 canTxID.all.TxID4=0;
 SJARst = 1;
 for(i = 0;i < 225;i++);
 SJARst = 0;
 for(i = 0;i < 225;i++);
 SJARst = 1;
 for(i = 0;i < 225;i++);
 REG_MOD = 0x01; 
 temp_data1 = REG_MOD;
 if((temp_data1 & 0x01)!=0) 
 {
 REG_MOD  = 0x05;
 REG_BTR0 = 0x87;
 REG_BTR1 = 0x0b4; 
 REG_OCR = 0x1a;
 REG_CDR = 0xc8; 
 REG_RBSA = 0x00;
 REG_ACR0 = 0x0ff;
 REG_ACR1 = 0x0ff;
 REG_ACR2 = 0x0ff;
 REG_ACR3 = 0x0ff;
 REG_AMR0 = 0x0ff;
 REG_AMR1 = 0x0ff;
 REG_AMR2 = 0x0ff;
 REG_AMR3 = 0x0ff;
 REG_IER = 0x0b;// enable TIE RIE DOIE
 }
 temp_data1 = REG_MOD;
 REG_MOD = temp_data1 & 0x0fe; 
 //_REG_CMD=0x01;
 
 EA=1;
 EX0=1;//enable ex0

 REG_TxIDBuffer0 = 0x88; //??? ???8  dsp:2no.,99,2,10,0xffffffe
 REG_TxIDBuffer1 = 0x00;
 REG_TxIDBuffer2 = 0x01;

 REG_TxIDBuffer3 = 0x02 ;
 REG_TxIDBuffer4 = 0x0f0;
 REG_DataBuffer1 = 0x03;
 REG_DataBuffer2 = 0x04;
 REG_DataBuffer3 = 0x05;
 REG_DataBuffer4 = 0x06;
 REG_DataBuffer5 = 0x07;
 REG_DataBuffer6 = 0x08;
 REG_DataBuffer7 = 0x09;
 REG_DataBuffer8 = 0x0a;

 REG_CMD = 0x10;//SelfReceptionRequest

for(;;)
{

 SPIComm();
}
}

void SPIComm()
{
	char temp;
	SPIOfflinTime++;
	if((ACKM==ACKS)||(SPIOfflinTime==255))
    {
	 	if(SPIOfflinTime==255)
	 	{
		 	SPIComIndicator=1;
	 	}
        else
		{
	    	SPIComIndicator=0;
		}

		SPIOfflinTime=0;
//	   	SS=1;
		SPDAT =sdata[0];
		temp = SPDAT ;
 		while ((SPSTA & 0x80) == 0);
		rdata1[0]=SPDAT;
//		SS=0;

       for(i = 0; i < FIFO_LEVEL; i++)
  	   {
//		SS=1;
		SPDAT =sdata[i];
 		while ((SPSTA & 0x80) == 0);
		rdata1[i+1]=SPDAT;
//		SS=0;
   	   }

  	   ACKM=!ACKS;
 	   if(rdata1[0]==0x5A)
       {
       	  Sum=0;
		  for(i=1;i<FIFO_LEVEL-1;i++)
		  {
		  	Sum += rdata1[i];
		  }

		  if((Sum & 0x0ff)==rdata1[FIFO_LEVEL-1])
		  {

		  }
       }
       sdata[0]=0x5A;

           Sum=0;
       for(i=1;i<FIFO_LEVEL-1;i++)
	   {
		  Sum += sdata[i];
	   }
	   sdata[FIFO_LEVEL-1]=Sum & 0x0ff;
     }
}

void EXINT0_isr()  interrupt 0 using 1
{
  SRcpy = REG_IFR;
  if(SRcpy & 0x02)
  {
  	
 REG_TxIDBuffer0 = 0x88; 
 REG_TxIDBuffer1 = 0x55;
 REG_TxIDBuffer2 = 0x55; 
 REG_TxIDBuffer3 = 0x55;
 REG_TxIDBuffer4 = 0x50;
  
 REG_DataBuffer1 = rdata1[1];
 REG_DataBuffer2 = rdata1[2];
 REG_DataBuffer3 = rdata1[3];
 REG_DataBuffer4 = rdata1[4];
 REG_DataBuffer5 = rdata1[5];
 REG_DataBuffer6 = rdata1[6];
 REG_DataBuffer7 = rdata1[7];
 REG_DataBuffer8 = rdata1[8];
 
  REG_CMD = 0x1;//TransmitionRequest  
  }
  
 if(SRcpy & 0x01)
 {
  canRxID.all.RxID1 = REG_RxIDBuffer1;
  canRxID.all.RxID2 = REG_RxIDBuffer2;
 
  canRxID.all.RxID3 = REG_RxIDBuffer3;
  canRxID.all.RxID4 = REG_RxIDBuffer4;

 sdata[1] = REG_DataBuffer1;
 sdata[2] = REG_DataBuffer2;
 sdata[3] = REG_DataBuffer3;
 sdata[4] = REG_DataBuffer4;
 sdata[5] = REG_DataBuffer5;
 sdata[6] = REG_DataBuffer6;
 sdata[7] = REG_DataBuffer7;
 sdata[8] = REG_DataBuffer8; 
  
 CANComIndicator=ON;
 REG_CMD = 0x4;
 }
 else
 {
   CANOfflinTime++;
   if(CANOfflinTime==255)
   {
       CANComIndicator=OFF;
   }
 }
   if(SRcpy & 0x08)
 {
   REG_CMD = 0x8;
 }
}