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抢答器设计实验程序,实现了将达的效果

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FL D:/暑假实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV_1K.vhdl 2006/05/06.04:37:04
FL f:/导师资料/教学/实验课文档/实验4/preemption/COV_CNT.vhdl 2006/05/05.18:50:44
FL D:/暑假实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/SEG_DISP.vhd 2006/05/06.04:56:18
FL F:/导师资料/教学/实验课文档/实验4/抢答器设计实验程序/PREEMPTION/DIV50.vhdl 2006/05/04.11:04:57
FL D:/暑假实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/JUDEG_PRO.vhdl 2006/05/08.13:23:04
FL F:/导师资料/教学/实验课文档/实验4/PREEMPTION/JUDEG_PRO.vhdl 2006/05/07.18:26:53
FL F:/导师资料/教学/实验课文档/实验4/PREEMPTION/DIV50.vhdl 2006/05/04.11:04:57
FL F:/导师资料/教学/实验课文档/实验4/PREEMPTION/DIV_1K.vhdl 2006/05/05.13:37:02
FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/COV_CNT.vhdl 2006/11/13.18:52:36
EN work/COV_CNT \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/COV_CNT.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/COV_CNT/BEHAVIORAL \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/COV_CNT.vhdl \
      EN work/COV_CNT
FL F:/导师资料/教学/实验课文档/实验4/抢答器设计实验程序/PREEMPTION/COV_CNT.vhdl 2006/05/06.22:57:28
FL F:/导师资料/教学/实验课文档/实验4/PREEMPTION/COV_CNT.vhdl 2006/05/06.22:57:28
FL F:/导师资料/教学/实验课文档/实验4/抢答器设计实验程序/PREEMPTION/DIV_1K.vhdl 2006/05/05.13:37:02
FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/PREEMPTION.vhdl 2006/11/13.18:48:04
EN work/PREEMPTION \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/PREEMPTION.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/PREEMPTION/BEHAVIORAL \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/PREEMPTION.vhdl \
      EN work/PREEMPTION CP DIV50         CP DIV_1K         CP COV_CNT \
      CP JUDEG_PRO      CP SEG_DISP
FL F:/导师资料/教学/实验课文档/实验4/PREEMPTION/PREEMPTION.vhdl 2006/05/07.18:17:35
FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/JUDEG_PRO.vhdl 2006/11/13.18:52:28
EN work/JUDEG_PRO \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/JUDEG_PRO.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/JUDEG_PRO/BEHAVIORAL \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/JUDEG_PRO.vhdl \
      EN work/JUDEG_PRO
FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV50.vhdl 2006/05/05.02:04:58
EN work/DIV50 \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV50.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/DIV50/BEHAVIORAL \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV50.vhdl \
      EN work/DIV50
FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV_1K.vhdl 2006/05/06.04:37:04
EN work/DIV_1K \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV_1K.vhdl \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/DIV_1K/BEHAVIORAL \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV_1K.vhdl \
      EN work/DIV_1K
FL F:/导师资料/教学/实验课文档/实验4/抢答器设计实验程序/PREEMPTION/JUDEG_PRO.vhdl 2006/05/07.22:23:03
FL D:/暑假实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/PREEMPTION.vhdl 2006/07/13.07:50:40
FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/SEG_DISP.vhd 2006/11/13.15:49:32
EN work/SEG_DISP \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/SEG_DISP.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/SEG_DISP/A \
      FL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/SEG_DISP.vhd \
      EN work/SEG_DISP
FL F:/导师资料/教学/实验课文档/实验4/抢答器设计实验程序/PREEMPTION/SEG_DISP.vhd 2006/05/05.13:56:17
FL D:/暑假实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/COV_CNT.vhdl 2006/05/07.13:57:30
FL F:/导师资料/教学/实验课文档/实验4/PREEMPTION/SEG_DISP.vhd 2006/05/05.13:56:17
FL D:/暑假实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV50.vhdl 2006/05/05.02:04:58
FL F:/导师资料/教学/实验课文档/实验4/抢答器设计实验程序/PREEMPTION/PREEMPTION.vhdl 2006/05/07.22:38:29