hdllib.ref

抢答器设计实验程序,实现了将达的效果

EN cov_cnt NULL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/COV_CNT.vhdl sub00/vhpl00
AR seg_disp a D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/SEG_DISP.vhd sub00/vhpl11
EN preemption NULL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/PREEMPTION.vhdl sub00/vhpl08
EN judeg_pro NULL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/JUDEG_PRO.vhdl sub00/vhpl02
EN seg_disp NULL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/SEG_DISP.vhd sub00/vhpl10
AR judeg_pro behavioral D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/JUDEG_PRO.vhdl sub00/vhpl03
AR div_1k behavioral D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV_1K.vhdl sub00/vhpl07
EN div50 NULL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV50.vhdl sub00/vhpl04
EN div_1k NULL D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV_1K.vhdl sub00/vhpl06
AR div50 behavioral D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/DIV50.vhdl sub00/vhpl05
AR preemption behavioral D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/PREEMPTION.vhdl sub00/vhpl09
AR cov_cnt behavioral D:/FPGA实验/实验/实验5_抢答器设计实验程序/抢答器设计实验程序/PREEMPTION/COV_CNT.vhdl sub00/vhpl01