omap2evm.c

OMAp2530 x-load source code

	__raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/

	__raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
	__raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80);  /* ADDR_MATCH_2 L*/

	/* IVA Changes */
	__raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
}

/**********************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP type, unlock the SRAM for general use.
 ***********************************************************/
void try_unlock_sram(void)
{
	int mode;

	/* if GP device unlock device SRAM for general use */
	mode = get_device_type();

	if ((mode == GP_DEVICE) || (mode == HS_DEVICE) 
		|| (mode == EMU_DEVICE)	|| (mode == TST_DEVICE)) {
	/* Secure or Emulation device - HS/E/T */
		SEC_generic();
	}
	return;
}

/**********************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 * - Called at time when only stack is available.
 **********************************************************/

int s_init(int skip)
{
	u32   rev;

	rev = get_cpu_rev();

	watchdog_init();
	try_unlock_sram();   
	muxSetupAll();
	delay(100);
	prcm_init();
	config_2430sdram_ddr(rev);
	delay(20000);
	peripheral_enable();
	return(0);
}

/*******************************************************
 * Routine: misc_init_r
 * Description: Init ethernet (done here so udelay works)
 ********************************************************/
int misc_init_r (void)
{
	return(0);
}

/****************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************/
static void watchdog_init(void)
{
#define GP (BIT8|BIT9)

	/* There are 4 watch dogs.  1 secure, and 3 general purpose.
	 * I would expect that the ROM takes care of the secure one,
	 * but we will try also.  Of the 3 GP ones, 1 can reset us
	 * directly, the other 2 only generate MPU interrupts.
	 */
	__raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
	wait_for_command_complete(WD2_BASE);
	__raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);

}

/******************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 ******************************************************/
static void wait_for_command_complete(unsigned int wd_base)
{
	int pending = 1;
	do {
		pending = __raw_readl(wd_base+WWPS);
	} while (pending);
}


/**********************************************
 * Routine: dram_init
 * Description: sets uboots idea of sdram size
 **********************************************/
int dram_init (void)
{
	return 0;
}
 
/*****************************************************************
 * Routine: peripheral_enable
 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
 ******************************************************************/
static void peripheral_enable(void)
{
	unsigned int v, if_clks=0, if_clks2 = 0, func_clks=0, func_clks2 = 0;

	/* Enable GP2 timer.*/
	if_clks |= BIT4;
	func_clks |= BIT4;
	v = __raw_readl(CM_CLKSEL2_CORE) | 0x4;	/* Sys_clk input OMAP24XX_GPT2 */
	__raw_writel(v, CM_CLKSEL2_CORE);

	__raw_writel(0x0, CM_CLKSEL_WKUP);

#ifdef CFG_NS16550
	/* Enable UART 1 & 3 clock */
	func_clks |= BIT21;
	func_clks2 |= BIT2;
	if_clks |= BIT21;
	if_clks2 |= BIT2;
#endif
	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
	__raw_writel(v,CM_ICLKEN1_CORE );
	v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2;    /* Interface clocks on */
	__raw_writel(v, CM_ICLKEN2_CORE);

	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
	__raw_writel(v, CM_FCLKEN1_CORE);
	v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2;  /* Functional Clocks on */
	__raw_writel(v, CM_FCLKEN2_CORE);

	delay(1000);
}

/* Do pin muxing for all the devices used in X-Loader */
#define MUX_VAL(OFFSET,VALUE)\
                __raw_writeb(VALUE, OMAP24XX_CTRL_BASE + OFFSET);
static void muxSetupAll(void)
{
/* UART 1*/\
	MUX_VAL(0x00B1, 0x1B)        /* uart1_cts- EN, HI, 3, ->gpio_32 */\
	MUX_VAL(0x00B2, 0x1B)        /* uart1_rts- EN, HI, 3, ->gpio_8 */\
	MUX_VAL(0x00B3, 0x1B)        /* uart1_tx- EN, HI, 3, ->gpio_9 */\
	MUX_VAL(0x00B4, 0x1B)        /* uart1_rx- EN, HI, 3, ->gpio_10 */\
	MUX_VAL(0x0107, 0x01)        /* ssi1_dat_tx- Dis, 1, ->uart1_tx */\
	MUX_VAL(0x0108, 0x01)        /* ssi1_flag_tx- Dis, 1, ->uart1_rts */\
	MUX_VAL(0x0109, 0x01)        /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */\
	MUX_VAL(0x010A, 0x01)        /* ssi1_dat_rx- Dis, 1, ->uart1_rx */\
/* SDRC */
	MUX_VAL(0x0054, 0x08)       /* sdrc_a14 - EN, HI, 3, ->gpio_0 */
	MUX_VAL(0x0055, 0x08)       /* sdrc_a13 - EN, HI, 3, ->gpio_1 */
	MUX_VAL(0x0056, 0x08)       /* sdrc_a12 - Dis, 0 */
	MUX_VAL(0x0046, 0x00)       /* sdrc_ncs1 - Dis, 0 */
	MUX_VAL(0x0048, 0x00)       /* sdrc_cke1 - Dis, 0 */
/* GPMC */
	MUX_VAL(0x0030, 0x18)       /* gpmc_clk - Dis, 0 */
	MUX_VAL(0x0031, 0x18)       /* gpmc_clk - Dis, 0 */
	MUX_VAL(0x0032, 0x18)       /* gpmc_ncs1- Dis, 0 */
	MUX_VAL(0x0033, 0x18)       /* gpmc_ncs2- Dis, 0 */
	MUX_VAL(0x0034, 0x18)       /* gpmc_ncs3- Dis, 3, ->gpio_24 */
	MUX_VAL(0x0035, 0x18)       /* gpmc_nc5- Dis, 0 */
	MUX_VAL(0x0036, 0x18)       /* gpmc_nc5- Dis, 0 */
	MUX_VAL(0x0037, 0x18)       /* gpmc_nc5- Dis, 0 */
	MUX_VAL(0x0038, 0x18)       /* gpmc_nc5- Dis, 0 */
	MUX_VAL(0x0039, 0x18)       /* gpmc_nc5- Dis, 0 */
	MUX_VAL(0x003a, 0x18)       /* gpmc_nc5- Dis, 0 */
	MUX_VAL(0x003b, 0x18)       /* gpmc_nc5- Dis, 0 */
	MUX_VAL(0x003c, 0x18)       /* gpmc_nc5- Dis, 0 */
	MUX_VAL(0x003d, 0x18)       /* gpmc_nc5- Dis, 0 */
	MUX_VAL(0x003e, 0x18)       /* gpmc_nc5- Dis, 0 */
	MUX_VAL(0x003f, 0x18)       /* gpmc_nc5- Dis, 0 */

/* GPMC mux for NAND access */
	MUX_VAL(0x0086, 0x18)       /* gpmc_a9 - EN, HI, 0*/
	MUX_VAL(0x0087, 0x18)       /* gpmc_a8 - EN, HI, 0*/
	MUX_VAL(0x0088, 0x18)       /* gpmc_a7 - EN, HI, 0*/
	MUX_VAL(0x0089, 0x18)       /* gpmc_a6 - EN, HI, 0*/
	MUX_VAL(0x008A, 0x18)       /* gpmc_a5 - EN, HI, 0*/
	MUX_VAL(0x008B, 0x18)       /* gpmc_a4 - EN, HI, 0*/
	MUX_VAL(0x008C, 0x18)       /* gpmc_a3 - EN, HI, 0*/
	MUX_VAL(0x008D, 0x18)       /* gpmc_a2 - EN, HI, 0*/
	MUX_VAL(0x008E, 0x18)       /* gpmc_a1 - EN, HI, 0*/
	MUX_VAL(0x008F, 0x18)       /* gpmc_d15 - EN,HI, 0*/
	MUX_VAL(0x0090, 0x18)       /* gpmc_d14 - EN, HI, 0*/
	MUX_VAL(0x0091, 0x18)       /* gpmc_d13 - EN, HI, 0*/
	MUX_VAL(0x0092, 0x18)       /* gpmc_d12 - EN, HI, 0*/
	MUX_VAL(0x0093, 0x18)       /* gpmc_d11 - EN, HI, 0*/
	MUX_VAL(0x0094, 0x18)       /* gpmc_d10 - EN, HI, 0*/
	MUX_VAL(0x0095, 0x18)       /* gpmc_d9 - EN, HI, 0 */
	MUX_VAL(0x0096, 0x18)       /* gpmc_d8 - EN, HI, 0*/
	MUX_VAL(0x0097, 0x18)       /* gpmc_d8 - EN, HI, 0*/
	MUX_VAL(0x0098, 0x18)       /* gpmc_d8 - EN, HI, 0*/
	MUX_VAL(0x0099, 0x18)       /* gpmc_d8 - EN, HI, 0*/
	MUX_VAL(0x009a, 0x18)       /* gpmc_d8 - EN, HI, 0*/
	MUX_VAL(0x009b, 0x18)       /* gpmc_d8 - EN, HI, 0*/
	MUX_VAL(0x009c, 0x18)       /* gpmc_d8 - EN, HI, 0*/
	MUX_VAL(0x009d, 0x18)       /* gpmc_d8 - EN, HI, 0*/
	MUX_VAL(0x009e, 0x18)       /* gpmc_d8 - EN, HI, 0*/
/* UART2 */
	MUX_VAL(0x00FF, 0x00)       /* uart2_cts- Dis, 0 */
	MUX_VAL(0x0100, 0x00)       /* uart2_rts- Dis, 0 */
	MUX_VAL(0x0101, 0x00)       /* uart2_tx- Dis, 0 */
	MUX_VAL(0x0102, 0x00)       /* uart2_rx- Dis, 0 */
/* UART3 */
	MUX_VAL(0x0126, 0x00)       /* uart3_cts_rctx- Dis, 0 */
	MUX_VAL(0x0127, 0x00)       /* uart3_rts_sd- Dis, 0 */
	MUX_VAL(0x0128, 0x1f)       /* uart3_tx_irtx- Dis, 0 */
	MUX_VAL(0x0129, 0x1f)       /* uart3_rx_irrx- Dis, 0 */
	MUX_VAL(0x0137, 0x01)       /* uart3_rts */
	MUX_VAL(0x0138, 0x01)       /* uart3_tx */
	MUX_VAL(0x0139, 0x01)       /* uart3_rx */
	MUX_VAL(0x00B5, 0x1B)       /*  */
	MUX_VAL(0x00B6, 0x1B)       /*  */
}

int nand_init(void)
{
	u32	rev;

	/* GPMC Configuration */
	rev  = get_cpu_rev();

	/* global settings */
	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
	__raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
	__raw_writel(0x001, GPMC_CONFIG);	/* set nWP, disable limited addr */

	__raw_writel(0, GPMC_CONFIG7_0);
	sdelay(1000);

	__raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1_0);
	__raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2_0);
	__raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3_0);
	__raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4_0);
	__raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5_0);
	__raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6_0);


	/* Enable the GPMC Mapping */
	__raw_writel(( ((OMAP24XX_GPMC_CS0_SIZE & 0xF)<<8) |
		     ((OMAP24XX_GPMC_CS0_MAP>>24) & 0x3F) |
		     (1<<6) ), GPMC_CONFIG7_0);
	sdelay(2000);
 	
	if (nand_chip()){
#ifdef CFG_PRINTF
		printf("Unsupported Chip!\n");
#endif
		return 1;
	}

	return 0;
}

/* optionally do something like blinking LED */
void board_hang (void)
{ while (0) {};}