omap2evm.c

OMAp2530 x-load source code

/*******************************************************************************
 * (C) Copyright 2007
 * Mistral, <www.mistralsolutions.com>
*******************************************************************************/
#include <common.h>
#include <asm/arch/omap2430.h>
#include <asm/arch/bits.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_info.h>
#include <asm/arch/clocks.h>

static void wait_for_command_complete( unsigned int wd_base );
static void watchdog_init( void );
static void peripheral_enable( void );
static void muxSetupAll( void );
static u32  get_cpu_rev( void );
static u32  get_device_type( void );
static void prcm_init( void );


/*******************************************************
 * Routine: delay
 * Description: spinning delay to use before udelay works
 ******************************************************/
static inline void delay( unsigned long loops )
{
	__asm__ volatile ("1:\n"
		"subs %0, %1, #1\n"
		"bne 1b":"=r" (loops):"0" (loops));
}

/*****************************************
 * Routine: board_init
 * Description: Early hardware init.
 *****************************************/
int board_init (void)
{
	return 0;
}

/******************************************
 * get_cpu_rev(void) - extract version info
 ******************************************/
u32 get_cpu_rev(void)
{
	u32 v;
	v = __raw_readl(TAP_IDCODE_REG);
	v = v >> 28;
	return(v+1); 
}

/*************************************************************
 *  get_device_type(): tell if GP/HS/EMU/TST
 *************************************************************/
u32 get_device_type(void)
{
	int mode;
	mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
	return(mode >>= 8);
}

/*************************************************************
 *  Helper function to wait for the status of a register
 *************************************************************/
u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
{
	u32 i = 0, val;
	do {
		++i;
		val = __raw_readl(read_addr) & read_bit_mask;
		if (val == match_value)
			return(1);
		if (i==bound)
			return(0);
	} while (1);
}

void config_2430sdram_ddr(u32 rev)
{
	int i;

	/* SYS Control register to allow sdrc_a12 to be connected at top level
	Need to ensure memory map allows 8-bit access to SYS 
	control PAD conf registers */
	__raw_writel(0x00080808, CONTROL_SDRC_A14);
	/* issues software reset of SDRAM interface */
	__raw_writel(0x0000000A, SDRC_SYSCONFIG);
	for (i = 0; i < 99; i++);
	__raw_writel(0x00000008, SDRC_SYSCONFIG);

	/* SDRC Sharing register, 16-bit SDRAM on data lane [16:0] 
           - CS0  pin tri-stated = 1 */
	__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
    
	/* ----- SDRC_CS0 Configuration --------- */
	/* SDRC_MCFG0 register */
	__raw_writel(0x02482011, SDRC_MCFG_0);

	/* SDRC_RFR_CTRL0 register */
	__raw_writel(0x0003DE01, SDRC_RFR_CTRL);

	/* SDRC_ACTIM_CTRLA0 register (optimise for clk = 133MHz) */
	__raw_writel(0x629B4487, SDRC_ACTIM_CTRLA_0);

	/* SDRC_ACTIM_CTRLB0 register */
	__raw_writel(0x00000014, SDRC_ACTIM_CTRLB_0);

	/* Disble Power Down of CKE cuz of 1 CKE on combo part */
	__raw_writel(0x81, SDRC_POWER);

	/* SDRC_Manual command register */
	__raw_writel(CMD_NOP, SDRC_MANUAL_0);
	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);

	/* SDRC MR0 register */
	__raw_writel(H4_2420_SDRC_MR_0_DDR, SDRC_MR_0);
	/* Burst length =4
	CAS latency = 3
	Write Burst = Read Burst
	Serial Mode */

	/* SDRC DLLA control register */
	/* Enable DLL, Load counter with 115 (middle of range) */

	/* Delay is 90 degrees */
	__raw_writel(0x0000730E, SDRC_DLLA_CTRL);

	/* Clear the Load DLL bit to use DLLA in lock mode */
	__raw_writel(0x0000730A, SDRC_DLLA_CTRL);

	/* SDRC DLLB control register 
	Enable DLL, Load counter with 128 (middle of range)
	Delay is 90 degrees */

	__raw_writel(0x0000730E, SDRC_DLLB_CTRL);

	/* Clear the Load DLL bit to use DLLB in lock mode */
	__raw_writel(0x0000730A, SDRC_DLLB_CTRL);
}


/*************************************************************
 * get_sys_clk_speed - determine reference oscillator speed
 *  based on known 32kHz clock and gptimer.
 *************************************************************/
u32 get_osc_clk_speed(u32 *shift)
{
	#define GPT_EN  ((0<<2)|BIT1|BIT0)      /* enable sys_clk NO-prescale /1 */
	#define GPT_CTR OMAP24XX_GPT2+TCRR      /* read counter address */
	u32 start, cstart, cend, cdiff, val;
	unsigned int v, if_clks=0, func_clks=0 ;

	if(__raw_readl(PRCM_CLKSRC_CTRL) & BIT7){    /* if currently /2 */
		*shift = 1;
	}else{
		*shift = 0;
	}

	/* enable timer2 */
	val = __raw_readl(CM_CLKSEL2_CORE) | 0x4;      /* mask for sys_clk use */
	__raw_writel(val, CM_CLKSEL2_CORE);            /* timer2 source to sys_clk */
	__raw_writel(BIT4, CM_ICLKEN1_CORE);           /* timer2 interface clock on */
	__raw_writel(BIT4, CM_FCLKEN1_CORE);           /* timer2 function clock on */
	/* Enable GP2 timer.*/
	if_clks |= BIT4;
	func_clks |= BIT4;
	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;	/* Interface clocks on */
	__raw_writel(v,CM_ICLKEN1_CORE );
	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
	__raw_writel(v, CM_FCLKEN1_CORE);
	__raw_writel(0, OMAP24XX_GPT2+TLDR);           /* start counting at 0 */
	__raw_writel(GPT_EN, OMAP24XX_GPT2+TCLR);      /* enable clock */
	/* enable 32kHz source */                      /* enabled out of reset */
	/* determine sys_clk via gauging */
	start = 20 + __raw_readl(S32K_CR);             /* start time in 20 cycles*/
	while(__raw_readl(S32K_CR) < start);           /* dead loop till start time */
	cstart = __raw_readl(GPT_CTR);                 /* get start sys_clk count */
	while(__raw_readl(S32K_CR) < (start+20));      /* wait for 40 cycles */
	cend = __raw_readl(GPT_CTR);                   /* get end sys_clk count */
	cdiff = cend - cstart;                         /* get elapsed ticks */
	/* based on number of ticks assign speed */
	if(cdiff > (19000 >> *shift))
		return(S38_4M);
	else if (cdiff > (15200 >> *shift))
		return(S26M);
	else if (cdiff > (13000 >> *shift))
		return(S24M);
	else if (cdiff > (9000 >> *shift))
		return(S19_2M);
	else if (cdiff > (7600 >> *shift))
		return(S13M);
	else
		return(S12M);
}

/*********************************************************************************
 * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
 *   -- called from SRAM
 *********************************************************************************/

void prcm_init()
{
	u32 div, speed, val, div_by_2;

	__raw_writel(0x80, PRCM_CLKSRC_CTRL);
	
	speed = get_osc_clk_speed(&div_by_2);
	if((speed > S19_2M) && (!div_by_2)){ /* if fast && /2 off, enable it */
		val = ~(BIT6|BIT7) & __raw_readl(PRCM_CLKSRC_CTRL);
		val |= (0x2 << 6); /* divide by 2 if (24,26,38.4) -> (12/13/19.2)  */
		__raw_writel(val, PRCM_CLKSRC_CTRL);
	}

	__raw_writel(0, CM_FCLKEN1_CORE);	/* stop all clocks to reduce ringing */
	__raw_writel(0, CM_FCLKEN2_CORE);	/* may not be necessary */
	__raw_writel(0, CM_ICLKEN1_CORE);
	__raw_writel(0, CM_ICLKEN2_CORE);

	__raw_writel(0xC3, CM_CLKEN_PLL);

	__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */
	__raw_writel(MPU_DIV, CM_CLKSEL_MPU);   /* set MPU divider */
	__raw_writel((2<<0)|(3<<5), CM_CLKSEL_DSP);   /* set dsp and iva dividers */
	__raw_writel(GFX_DIV, CM_CLKSEL_GFX);   /* set gfx dividers */
	__raw_writel(0x6, CM_CLKSEL_MDM);   /* set mdm dividers */
	div = 0x02100846;//dss1 clock
	__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/SSi dividers */
	delay(1000);
	__raw_writel(0x0114ac00, CM_CLKSEL1_PLL);
	__raw_writel(0x0, CM_CLKSEL_WKUP);
        

	/*13MHz apll src, PRCM 'x' DPLL rate */

	/*Valid the configuration */
	__raw_writel(0x00000001, PRCM_CLKCFG_CTRL);
	delay(1000);

	/* set up APLLS_CLKIN per crystal */
	__raw_writel(0xcf, CM_CLKEN_PLL);   /* enable apll */
	wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);/* wait for apll lock */
	delay(200000);

	__raw_writel(0xFFFF800F, CM_FCLKEN1_CORE);
	__raw_writel(0xFFFFFFFF, CM_FCLKEN2_CORE);
	__raw_writel(0xFFFF800F, CM_ICLKEN1_CORE);
	__raw_writel(0xFFFFFFFF, CM_ICLKEN2_CORE);
}


void SEC_generic(void)
{
/* Permission values for registers -Full fledged permissions to all */
#define UNLOCK_1 0xFFFFFFFF
#define UNLOCK_2 0x00000000
#define UNLOCK_3 0x0000FFFF
	/* Protection Module Register Target APE (PM_RT)*/
	__raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); /* REQ_INFO_PERMISSION_1 L*/
	__raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50);  /* READ_PERMISSION_0 L*/
	__raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58);  /* WRITE_PERMISSION_0 L*/
	__raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); /* ADDR_MATCH_1 L*/


	__raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
	__raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/