omap2430sdp.c

OMAp2530 x-load source code

/*
 * (C) Copyright 2004-2005
 * Texas Instruments, <www.ti.com>
 * Jian Zhang <[e-mail]>
 * Richard Woodruff <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/arch/omap2430.h>
#include <asm/arch/bits.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_info.h>
#include <asm/arch/clocks.h>

static void wait_for_command_complete(unsigned int wd_base);
static void watchdog_init(void);
static void peripheral_enable(void);
static void muxSetupAll(void);
static u32  get_cpu_rev(void);
static u32  get_device_type(void);
static void prcm_init(void);


/*******************************************************
 * Routine: delay
 * Description: spinning delay to use before udelay works
 ******************************************************/
static inline void delay (unsigned long loops)
{
	__asm__ volatile ("1:\n"
					  "subs %0, %1, #1\n"
					  "bne 1b":"=r" (loops):"0" (loops));
}

/*****************************************
 * Routine: board_init
 * Description: Early hardware init.
 *****************************************/
int board_init (void)
{
	return 0;
}

/******************************************
 * get_cpu_rev(void) - extract version info
 ******************************************/
u32 get_cpu_rev(void)
{
        u32 v;
        v = __raw_readl(TAP_IDCODE_REG);
        v = v >> 28;
        return(v+1);  /* currently 2422 and 2420 match up */
}

/*************************************************************
 *  get_device_type(): tell if GP/HS/EMU/TST
 *************************************************************/
u32 get_device_type(void)
{
        int mode;
        mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
        return(mode >>= 8);
}

/*************************************************************
 *  Helper function to wait for the status of a register
 *************************************************************/
u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
{
        u32 i = 0, val;
        do {
                ++i;
                val = __raw_readl(read_addr) & read_bit_mask;
                if (val == match_value)
                        return(1);
                if (i==bound)
                        return(0);
        } while (1);
}

/*************************************************************
 *  Support for multiple type of memory types
 *************************************************************/
#ifdef CFG_SDRAM_DDR
void
config_sdram_ddr(u32 rev)
{
	/* ball D11, mode 0 */
	__raw_writeb(0x08, 0x48000032);

	/* SDRC_CS0 Configuration */
	__raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
	__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);

	__raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
	__raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0);
	__raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0);

	/* Manual Command sequence */
	__raw_writel(CMD_NOP, SDRC_MANUAL_0);
	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);


	/* 
	 * CS0 SDRC Mode Register
	 * Burst length = 4 - DDR memory
	 * Serial mode
	 * CAS latency = 3 
	 */
	__raw_writel(0x00000032, SDRC_MR_0);

 	/* SDRC DLLA control register */
	/* Delay is 90 degrees */
	/* Enable DLL, Load counter with 115 (middle of range) */ 
	__raw_writel(0x00000008, SDRC_DLLA_CTRL);	// ES2.x
	/* Enable DLL, Load counter with 128 (middle of range) */ 
	__raw_writel(0x00000008, SDRC_DLLB_CTRL);	// ES2.x

}
#endif // CFG_SDRAM_DDR

#ifdef CFG_SDRAM_COMBO 
void
config_sdram_combo(u32 rev)
{

	u32 dllctrl=0;

        /* ball C12, mode 0 */
        __raw_writeb(0x00, 0x480000a1);
        /* ball D11, mode 0 */
        __raw_writeb(0x00, 0x48000032);
        /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */
        __raw_writeb(0x00, 0x480000a3);

        /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */
        __raw_writel(0x00000012, SDRC_SYSCONFIG);
        wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */
        __raw_writel(0x00000000, SDRC_SYSCONFIG);

        /* SDRCTriState: no Tris */
        /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
	if (rev == CPU_2420_2422_ES1)
	        __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
	else
       		__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);


        /* CS0 SDRC Memory Configuration, */
        /* DDR-SDRAM, External SDRAM is x32bit, */
        /* Configure to MUX9: 1x8Mbx32  */
        __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0);
        __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
        __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
	
	/* This is reqd only for ES1 */
	if (rev == CPU_242X_ES1)
        	__raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);

        /* Manual Command sequence */
        __raw_writel(CMD_NOP, SDRC_MANUAL_0);
	delay(5000);
        __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
        __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
        __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);

        /* CS0 SDRC Mode Register */
        /* Burst length = 4 - DDR memory */
        /* Serial mode */
        /* CAS latency = 3  */
        __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0);

        /* CS1 SDRC Memory Configuration, */
        /* DDR-SDRAM, External SDRAM is x32bit, */
        /* Configure to MUX9: 1x8Mbx32 */
        __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1);
        __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1);
        __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1);
	/* This is reqd only for ES1 */
	if (rev == CPU_242X_ES1)
        	__raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4);

        /* Manual Command sequence */
        __raw_writel(CMD_NOP, 0x680090d8);
        __raw_writel(CMD_PRECHARGE, 0x680090d8);
        __raw_writel(CMD_AUTOREFRESH, 0x680090d8);
        __raw_writel(CMD_AUTOREFRESH, 0x680090d8);

        /* CS1 SDRC Mode Register */
	/* Burst length = 4 - DDR memory */
        /* Serial mode */
        /* CAS latency = 3 */
        __raw_writel(H4_2422_SDRC_MR_0_DDR, 0x680090b4);

        /* SDRC DLLA control register */
        /* Delay is 90 degrees */

	if (rev == CPU_242X_ES1)
		dllctrl = (BIT0|BIT3);
	else
		dllctrl = BIT0;		

        if (rev == CPU_2420_2422_ES1) {
                /* Enable DLL, Load counter with 115 (middle of range) */
                __raw_writel(0x00007306, SDRC_DLLA_CTRL);
                __raw_writel(0x00007302, SDRC_DLLA_CTRL);
                /* Enable DLL, Load counter with 128 (middle of range)  */
                __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
                __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
        }
        else {
                /* Enable DLL, Load counter with 115 (middle of range) */
                __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);   // ES2.x
                __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL);   // ES2.x
               // __raw_writel(0x00009808, SDRC_DLLA_CTRL);   // ES2.x
                /* Enable DLL, Load counter with 128 (middle of range) */
                __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL);   // ES2.x ?
                __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL);   // ES2.x
                //__raw_writel(0x00009808, SDRC_DLLB_CTRL);   // ES2.x
        }
}

#endif // CFG_SDRAM_COMBO

#ifdef CFG_2430SDRAM_DDR
void
config_2430sdram_ddr(u32 rev)
{
	u32 dllstat, dllctrl;

        __raw_writel(0x00000012, SDRC_SYSCONFIG);
        wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */
        __raw_writel(0x00000000, SDRC_SYSCONFIG);

	/* Chip-level shared interface management */
	/* SDRCTriState: no Tris */
	/* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
	/* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */
	__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);

	/* CS0 SDRC Memory Configuration, */
	/* DDR-SDRAM, External SDRAM is x32bit, */
	/* Configure to MUX14: 32Mbx32 */
	__raw_writel(SDP_2430_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
	__raw_writel(SDP_2430_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
	__raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);

	__raw_writel(H4_2420_SDRC_RFR_CTRL, SDRC_RFR_CTRL);

	/* Manual Command sequence */
	__raw_writel(CMD_NOP, SDRC_MANUAL_0);
	delay(5000);
	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
 
	/* CS0 SDRC Mode Register */
	/* Burst length = 2 - SDR memory */
	/* Serial mode */
	/* CAS latency = 3  */
	__raw_writel(H4_2420_SDRC_MR_0_DDR, SDRC_MR_0);

	/* Set up SDRC DLL values for 2430 DDR */
	dllctrl = (SDP_2430_SDRC_DLLAB_CTRL & ~BIT2); /* set target ctrl val */
	__raw_writel(dllctrl, SDRC_DLLA_CTRL);	/* set lock mode */
	__raw_writel(dllctrl, SDRC_DLLB_CTRL);	/* set lock mode */
	delay(0x1000); /* time to track to center */	
	dllstat = __raw_readl(SDRC_DLLA_STATUS) & 0xFF00; /* get status */
	dllctrl = (dllctrl & 0x00FF) | dllstat | BIT2; /* build unlock value */
	__raw_writel(dllctrl, SDRC_DLLA_CTRL);	/* set unlock mode */
	__raw_writel(dllctrl, SDRC_DLLB_CTRL);	/* set unlock mode */
}
#endif // CFG_2430SDRAM_DDR

#ifdef CFG_SDRAM_STACKED 
void
config_sdram_stacked(u32 rev)
{

	/* Pin Muxing for SDRC */
	__raw_writeb(0x00, 0x480000a1);	/* mux mode 0 (CS1) */
	__raw_writeb(0x00, 0x480000a3);	/* mux mode 0 (CKE1) */
	__raw_writeb(0x00, 0x48000032);	/* connect sdrc_a12 */
	__raw_writeb(0x00, 0x48000031);	/* connect sdrc_a13 */

	/* configure sdrc 32 bit for COMBO ddr sdram */
	__raw_writel(0x00000010, SDRC_SYSCONFIG);	/* no idle ack and RESET enable */
	delay(200000);
	__raw_writel(0x00000010, SDRC_SYSCONFIG);	/* smart idle mode */

	/* SDRC_SHARING */
	/* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */
	//__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);

	__raw_writel(0x00004900, SDRC_SHARING);

	/* SDRC_CS0 Configuration */
	/* None for ES2.1 */

	/*  SDRC_CS1 Configuration */
	__raw_writel(0x00000000, SDRC_CS_CFG);	/* Remap CS1 to 0x80000000 */

	/* Disable power down of CKE */
	__raw_writel(0x00000085, SDRC_POWER);

	__raw_writel(0x01A02019, SDRC_MCFG_1);	/* SDRC_MCFG1 */
	__raw_writel(0x0003DD03, SDRC_RFR_CTRL1);	/* SDRC_RFR_CTRL1 */
	__raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1);	/* SDRC_ACTIM_CTRLA0 */
	__raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1);	/* SDRC_ACTIM_CTRLB0 */

	/*Manual Command sequence */
	__raw_writel(0x00000000, 0x680090D8);
	__raw_writel(0x00000001, 0x680090D8);
	__raw_writel(0x00000002, 0x680090D8);
	__raw_writel(0x00000002, 0x680090D8);

	/* CS0 SDRC Mode Register */
	/* Burst length = 4 - DDR memory */
	/* Serial mode */
	/* CAS latency = 3  */
	__raw_writel(0x00000032, 0x680090B4);
	__raw_writel(0x00000020, 0x680090BC);	/* weak-strength driver */

 	/* SDRC DLLA control register */
	/* Delay is 90 degrees */
	if (rev == CPU_2420_2422_ES1) {
		/* Enable DLL, Load counter with 115 (middle of range) */ 
		__raw_writel(0x00007302, SDRC_DLLA_CTRL);
		/* Enable DLL, Load counter with 128 (middle of range) */ 
		__raw_writel(0x00007302, SDRC_DLLB_CTRL);
	}
	else {
		/* Enable DLL, Load counter with 115 (middle of range) */ 
		__raw_writel(0x00003108, SDRC_DLLA_CTRL);	// ES2.x
		/* Enable DLL, Load counter with 128 (middle of range) */ 
		__raw_writel(0x00003108, SDRC_DLLB_CTRL);	// ES2.x
	}
}
#endif // CFG_SDRAM_STACKED

/*************************************************************
 * get_sys_clk_speed - determine reference oscillator speed
 *  based on known 32kHz clock and gptimer.
 *************************************************************/
u32 get_osc_clk_speed(u32 *shift)
{
#define GPT_EN  ((0<<2)|BIT1|BIT0)      /* enable sys_clk NO-prescale /1 */
#define GPT_CTR OMAP24XX_GPT2+TCRR      /* read counter address */
        u32 start, cstart, cend, cdiff, val;
	unsigned int v, if_clks=0, func_clks=0 ;



        if(__raw_readl(PRCM_CLKSRC_CTRL) & BIT7){    /* if currently /2 */